Embedded Hyperchaotic Generators: A Comparative Analysis
In this paper, we present a comparative analysis of FPGA implementation performances, in terms of throughput and resources cost, of five well known autonomous continuous hyperchaotic systems. The goal of this analysis is to identify the embedded hyperchao
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Abstract In this paper, we present a comparative analysis of FPGA implementation performances, in terms of throughput and resources cost, of five well known autonomous continuous hyperchaotic systems. The goal of this analysis is to identify the embedded hyperchaotic generator which leads to designs with small logic area cost, satisfactory throughput rates, low power consumption and low latency required for embedded applications such as secure digital communications between embedded systems. To implement the four-dimensional (4D) chaotic systems, we use a new structural hardware architecture based on direct VHDL description of the forth order Runge-Kutta method (RK-4). The comparative analysis shows that the hyperchaotic Lorenz generator provides attractive performances compared to that of others. In fact, its hardware implementation requires only 2067 CLB-slices, 36 multipliers and no block RAMs, and achieves a throughput rate of 101.6 Mbps, at the output of the FPGA circuit, at a clock frequency of 25.315 MHz with a low latency time of 316 ns. Consequently, these good implementation performances offer to the embedded hyperchaotic Lorenz generator the advantage of being the best candidate for embedded communications applications.
S. Sadoudi () M.S. Azzaz Communication Systems Laboratory, Ecole Militaire Polytechnique, BP 17, Bordj El Bahri, Algiers, 16000, Algeria e-mail: [email protected] C. Tanougast A. Dandache Interfaces, Sensors and Microelectronic Laboratory, Paul Verlaine University of Metz, 7 Rue Marconi Metz, 57070, France e-mail: [email protected] S.G. Stavrinides et al. (eds.), Chaos and Complex Systems, DOI 10.1007/978-3-642-33914-1 37, © Springer-Verlag Berlin Heidelberg 2013
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1 Introduction Secure data transmission is a significant subject for which various encryption schemes have been proposed. Among them, we have considered digital encryption based chaos, which can be synchronized and promises new and efficient way to deal with the problem of fast and highly secure data transmission and communications. Indeed, digital chaotic cipher (which are very sensitive to small variations of their initial conditions and parameters) present unpredictability and ergodicity [1] properties and have shown some attractive properties in terms of security, complexity, speed, computing power and computational overhead, etc. Generally, the strategy of the chaos-based secure communications approach implements a cipher key generator based on a chaotic generator, then the generated chaotic keys are used directly to encrypt the plaintext. Recently, several behavioral structures of chaotic systems are implemented in FPGA technology [2]. They are used for designing chaotic hardware key generation for data encryption systems. However, these chaotic generators are easily attacked by a simple display of their attractors. Although chaotic signals are non-periodic, uncorrelated and appear random in the time domain, they are characterized by specific attractors which can be used
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