Encapsulation of graphene interconnects with 2D Layered Insulator for improved performance
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Encapsulation of graphene interconnects with 2D Layered Insulator for improved performance Nikhil Jain and Bin Yu* College of Nanoscale Science & Engineering, State University of New York, 257 Fuller Road, Albany, NY 12203, U.S.A. ABSTRACT The key material behavior of graphene, a single layer of carbon lattice, is extremely sensitive to its dielectric environment. We demonstrate improvement in electronic performance of graphene nanowire interconnects with full encapsulation by lattice-matching, chemically inert, 2D layered insulator hexagonal boron nitride (h-BN). A novel layer-based transfer technique is developed to construct the h-BN/MLG/h-BN heterostructures. The encapsulated graphene wires are characterized and compared with that on SiO2 or h-BN substrate without top passivating hBN layer. Significant improvements in maximum current-carrying density, breakdown threshold, and maximum power density in encapsulated graphene wires are observed. These critical improvements are achieved without compromising the carrier transport characteristics in graphene. Furthermore, graphene wires exhibit electrical behavior much less insensitive to ambient conditions, as compared with the non-passivated ones. Overall, h-BN/graphene/h-BN heterostructure presents a robust material platform towards the implementation of highperformance carbon-based interconnects. INTRODUCTION Interconnect wire systems need to keep pace with advancements in miniaturization of integrated circuits [1]. The current industry standard for lateral interconnects is copper which has its limitations at aggressively reduced dimensions that are bound to be encountered below the 13 nm node. These limitations include degradation in resistivity and hence increased propagation (RC) delay due to the effect of increased carrier scattering [2]. Another issue that copper interconnects face with reducing the pitch is that of crosstalk [3]. The current density in interconnects is expected to rise beyond the electromigration-induced failure limit of copper (106 A/cm2) [4]. These critical issues while scaling down of copper interconnects are presenting an ever increasing demand for new/hybrid material systems, novel fabrication processes, and innovative integration/packaging strategies for wiring applications. We explore the possibility of using graphene as an alternative material for interconnects in the post-Cu era. Graphene, a two-dimensional (2D) allotrope of carbon with strong in-plane sp2 bonding, exhibits several attractive material/electrical properties including long-range ballistic transport, superb thermal conductivity, electromechanical robustness, and high current density [5]. While it was initially obtained by micromechanical exfoliation process which is unsuitable for in-line processes, growth methods have now been developed that yield large-area, high-quality graphene using fab-compatible processes like chemical-vapor-deposition (CVD). This makes graphene an attractive material for on-chip interconnects. However, since graphene is a 2-D material, a thin sh
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