Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface
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Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface Joel Barnett, N. Moumena, J. Gutt, M. Gardnerb, C. Huffmanc, P. Majhid, J.J. Peterson, S. Gopalan, B. Foran, H.-J. Lie, B.H. Leea, G. Bersuker, P. M. Zeitzoff, G.A. Brown, P. Lysaght, C. Young, R.W. Murtoc, and H. R. Huff, International SEMATECH, Austin, TX. a IBM Assignee, bAMD assignee, cTexas Instruments assignee, dPhilips assignee, eInfineon assignee ABSTRACT We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces. INTRODUCTION As transistor sizes continue to shrink, the gate dielectric’s equivalent oxide thickness (EOT) must scale below 1.0 nm to increase the gate stack capacitance density. With decreasing gate oxide thickness, however, direct tunneling becomes a major device issue as it contributes to leakage current and, subsequently, to increased standby power consumption [1]. By increasing the permitivity of the gate dielectric, the physical thickness of the gate may be increased, providing reduced leakage current with comparable device capacitance. Researchers have recently been studying hafnium based high-k dielectrics as an alternative to SiO2 [2]. However, hafnium films deposited directly on hydrogen terminated silicon surfaces have not achieved electrical performance comparable to that achieved with SiO2. In order to achieve sub-nm EOT with high-k dielectrics while meeting the requirements of saturation current, transconductance and mobility, the interfacial-layer thickness and physicochemical properties must be therefore be optimized [3]. Typically, chemical oxides and thinly grown thermal oxides are used as a starting surface for the high-k deposition but these films can be problematic – the chemical oxide does not appear robust enough and it is very difficult to grow very thin and uniform (0.5 nm) thermal oxides. In this work, we describe a process (patent pending) in which a 2 nm in-situ-steamgenerated (ISSG) thermal oxide is grown and then etched back in a controlled manner to achieve both a uniform, robust interface for high-k deposition and significant improvements in device electrical performance compared to more conventional surface preparation techniques. In particular, this approach in combination with an HfSiO dielectric film and a TiN gate electrode resulted in EOT's as low as 0.87 nm and increased Idsat and mobility. EXPERIMENT PROCEDURES Evaluation of the impact of the various cleans on device performance and reliability was accomplished using transistors of various dimensions. Beginning with a 200 mm, (100) ori
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