Extreme Statistics in Nanoscale Memory Design
Extreme Statistics in Nanoscale Memory Design brings together some of the world’s leading experts in statistical EDA, memory design, device variability modeling and reliability modeling, to compile theoretical and practical results in one complete referen
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Series Editor Anantha Chandrakasan Massachusetts Institute of Technology Cambridge, Massachusetts
For further volumes, go to http://www.springer.com/series/7236
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Amith Singhee
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Rob A. Rutenbar
Editors
Extreme Statistics in Nanoscale Memory Design
Editors Amith Singhee IBM Thomas J. Watson Research Center 1101 Kitchawan Road, Route 134 Yorktown Heights, NY 10598, USA [email protected]
Rob A. Rutenbar Department of Computer Science University of Illinois at Urbana-Champaign 201 North Goodwin Avenue Urbana, IL 61801, USA [email protected]
ISSN 1558–9412 ISBN 978-1-4419-6605-6 e-ISSN 978-1-4419-6606-3 DOI 10.1007/978-1-4419-6606-3 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2010934212 # Springer ScienceþBusiness Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the New York, written permission of the publisher (Springer ScienceþBusiness Media, LLC, 233 Spring Street NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer ScienceþBusiness Media (www.springer.com)
Preface
Knowledge exists: you only have to find it
VLSI design has come to an important inflection point with the appearance of large manufacturing variations as semiconductor technology has moved to 45 nm feature sizes and below. If we ignore the random variations in the manufacturing process, simulation-based design essentially becomes useless, since its predictions will be far from the reality of manufactured ICs. On the other hand, using design margins based on some traditional notion of worst-case scenarios can force us to sacrifice too much in terms of power consumption or manufacturing cost, to the extent of making the design goals even infeasible. We absolutely need to explicitly account for the statistics of this random variability, to have design margins that are accurate so that we can find the optimum balance between yield loss and design cost. This discontinuity in design processes has led many researchers to develop effective methods of statistical design, where the designer can simulate not just the behavior of the nominal design, but the expected statistics of the behavior in manufactured ICs. Memory circuits tend to be the hardest hit by the problem of these random variations because of their high replication count on any single chip, which demands a very high statistical quality from the product. Requirements of 5–6s (0.6 ppm to 2 ppb failure rate) are very common for today’s SRAM caches of 1–10 Mb range, a
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