System Reduction for Nanoscale IC Design
This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and devic
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Peter Benner Editor
System Reduction for Nanoscale IC Design
MATHEMATICS IN INDUSTRY Editors Hans Georg Bock Frank de Hoog Avner Friedman Arvind Gupta André Nachbin Tohru Ozawa William R. Pulleyblank Torgeir Rusten Fadil Santosa Jin Keun Seo Anna-Karin Tornberg
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More information about this series at http://www.springer.com/series/4650
Peter Benner Editor
System Reduction for Nanoscale IC Design
123
Editor Peter Benner Max Planck Institute for Dynamics of Complex Technical Systems Magdeburg, Germany
ISSN 1612-3956 Mathematics in Industry ISBN 978-3-319-07235-7 DOI 10.1007/978-3-319-07236-4
ISSN 2198-3283 (electronic) ISBN 978-3-319-07236-4 (eBook)
Library of Congress Control Number: 2017942739 Mathematics Subject Classification (2010): 94-02, 65L80, 94C05 © Springer International Publishing AG 2017 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer International Publishing AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
Preface
The ongoing miniaturization of devices like transistors used in integrated circuits (ICs) has led to feature sizes on the nanoscale. The Intel Core 2 (Yorkfield), first presented in 2007, was produced using 45 nm technology. Recently, production has reached 14 nm processes, e.g., in the Intel Broadwell, Skylake, and Kaby Lake microprocessors. Although the main principles in IC design and production are those of microelectronics, nowadays, one therefore speaks of nanoelectronics. With miniaturization now reaching double-digit nanometer length scales and the huge number of semiconductor devices employed, which result in a correspondingly significant rise in integration density, the influence of the wiring and supply networks (interconnect and power grids) on the physical behavi
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