Fabrication and characterization of metal-ferroelectric-insulator-Si diodes and transistors with different HfSiON buffer
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Kenji Maruyama Fujitsu Laboratories Ltd., Morinosato-Wakamiya, Atsugi 243-0197, Japan (Received 27 February 2008; accepted 26 June 2008)
Metal-ferroelectric-insulator-Si (MFIS) structures using HfSiON as buffer layers were fabricated, and the impact of buffer layer thickness on the electrical properties of the MFIS devices was investigated. HfSiON films with thickness ranging from 1 to 4 nm were deposited by electron beam evaporation, which exhibited much reduced leakage current when compared to that of SiO2 with the same equivalent oxide thickness. From the viewpoint of polarization and charge injection, the flatband voltage and memory window width dependent on the sweeping voltages were discussed for the MFIS diodes with 1-, 2-, and 4-nm-thick HfSiON buffer layers. Small leakage current as well as excellent long-term data retention characteristics were found for all of these samples. It was also found that MFIS diodes with 2-nm-thick HfSiON buffer layer have the largest memory window width. Ferroelectric-gate transistors fabricated with a Pt/SBT(300nm)/HfSiON (2 nm)/Si gate structure showed a memory window of 0.8 V and a high drain current on/off ratio of 108 for the gate voltage sweep between +4 and −4 V. All of these excellent electrical properties proved that HfSiON acts as an excellent barrier for suppressing both leakage current and atomic interdiffusion.
I. INTRODUCTION
Ferroelectric-gate field-effect transistors (FETs) have attracted much attention over the past decades for memory applications, with their interesting features such as non-volatile data storage, non-destructive data read out, high operation speed, and high packing density.1 However, since it is difficult to form a ferroelectric– semiconductor interface with good electrical properties, no commercially available devices have been fabricated yet. To solve this interface problem, an insulating buffer layer is often inserted between a ferroelectric film and Si substrate to form metal-ferroelectric-insulator-semiconductor (MFIS) structures.2–12 A suitable buffer layer is expected to provide a good electronic interface between the buffer layer and the silicon substrate, and to minimize the charge injection and the voltage drop across it.1 A useful method to minimize the voltage drop across the buffer layer is to choose materials with highdielectric constant and good thermal stability between
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Address all correspondence to this author. e-mail: [email protected] DOI: 10.1557/JMR.2008.0336 J. Mater. Res., Vol. 23, No. 10, Oct 2008
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silicon and the buffer layer. From this consideration, high-dielectric constant materials such as Si 3N4,2,3 ZrO2,4 LaAlO3,5,6 Hf–Al–O,7,8 HfO2,9,10 HfTaO,11,12 etc. have been extensively studied as candidate buffer layers in the MFIS structures. Another possible method for decreasing the voltage drop across the buffer layer is to decrease the thickness of the buffer layer, which will increase its capacitance. If these methods are used, the voltage drop acr
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