Fabrication and Electronic Characteristics of Silicon Nanowire MOSFETs
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1080-O12-02
Fabrication and Electronic Characteristics of Silicon Nanowire MOSFETs Hironori Yoshioka1, Yuichiro Nanen1, Jun Suda1, and Tsunenobu Kimoto1,2 1 Department of Electronic Science and Engineering, Kyoto University, Kyotodaigaku-katsura, Nishikyo, Kyoto, 615-8510, Japan 2 Photonics and Electronics Science and Engineering Center, Kyoto University, Kyotodaigakukatsura, Nishikyo, Kyoto, 615-8510, Japan ABSTRACT The n-type silicon nanowire MOSFETs with a nanowire shape being triangular or trapezoidal, have been fabricated on SOI substrates and characterized. The height and bottomwidth of the triangular nanowire has been 10 nm and 19 nm, respectively. The devices have shown good gate control, such as a nearly ideal subthreshold slope of 63 mV/decade, high Ion/Ioff ratio of 107, and small drain-induced barrier lowering of 5 mV/V at room temperature. The low field mobility of triangular nanowire has been estimated to be 130 cm2/V·s and shown no difference with the change of the nanowire shape and direction within the investigated range.
INTRODUCTION Large scale integrated circuits (LSIs) have shown improving performance by reducing the size in accordance with the scaling law so far. The technology node has reached to less than 100 nm, and the scaling law is facing limitations by several fundamental problems like gate leakage current, heat generation, and short channel effect. Therefore, new device structures or materials are intensively needed to break the limits of conventional Si devices. MOSFETs using Si nanowires are one of the most promising candidates for next generation LSIs because they can effectively suppress the short channel effect. Several groups have reported fabrication of the Si nanowire MOSFETs [1-4] and the excellent gate control characteristics have been demonstrated [1, 2]. High mobility is still important for the nanowire MOSFETs to increase the drain current as well as switching speed. There are several factors to affect the mobility of nano size Si. The band structure is different from that of bulk owing to quantum confinement effect, by which the effective mass of electrons can be decreased by utilizing proper direction of the nanowire [5]. Intervalley scattering, which most severely degrades the electron mobility of bulk Si above room temperature, would decrease as a result of splitting of the six equivalent valleys of the bulk conduction band. Strain also have an effect on the mobility of nanowire (e.g., it was reported that hole mobility can be increased under compressive strain [6]). On the other hand, it was reported that carrier scattering induced by interface fluctuation reduced the electron mobility [7]. In this study, n-type Si nanowire MOSFETs have been fabricated on silicon on insulator (SOI) substrates. The low field mobility of the nanowire MOSFETs has been investigated in the wide temperature range from 98 to 421 K.
DEVICE FABRICATION SOI with the top Si being 340 nm-thick/{001}/n-type/1~2 Ω·cm and buried SiO2 thickness being 2 μm, was thinned to 39 nm by sacrificial oxida
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