Fabrication and Evaluation of 3D Packages with Through Hole Via
- PDF / 659,524 Bytes
- 8 Pages / 612 x 792 pts (letter) Page_size
- 41 Downloads / 195 Views
0970-Y05-06
Fabrication and Evaluation of 3D Packaging with Through Hole Via Dong Min Jang1, Kwang Yong Lee2, Chung Hyun Ryu1, Byeong Hoon Cho1, Tae Sung Oh2, Joung Ho Kim1, Won Jong Lee1, and Jin Yu1 1 CEPM, KAIST, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of 2 CEPM, Hongik University, Mapogu Sangsudong 72-1, Seoul, 121-791, Korea, Republic of
ABSTRACT System in package (SiP) is a superb candidate to enhance the area efficiency and performance of electronic packaging. Here, recent work on stacked chip type 3D SiP with vertically interconnected through hole vias are reported. The process includes; formation of 50um-diameter via holes, conformal deposition of SiO2 dielectric layer, deposition of Ta and Cu barrier layers, via filling by Cu electroplating, Cu/Sn bump formation for multi-chip stacking, and finally chip-to-PCB bonding using Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3D SiP stacked up to 10 layers was successfully fabricated. A high frequency electrical model of the through hole via was proposed and the model parameters were extracted from measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. Contact resistances of Cu via and bump joint were presented. INTRODUCTION As portable electronic products such as cellular phones, PDA, and digital cameras become smaller and require more functions, three dimensional (3D) stack packages have been extensively studied in recent years [1-6]. 3D stack packages were initially developed for memory packages with a stack of a flash memory and a SDRAM for the cellular phone, which had various advantages such as improvement of electrical performance and cost reduction as well as size and weight reduction [7]. In conventional 3D packages, wire bonding has been used to interconnect I/O pads of the stacked IC chips to the circuit board. However, wire bonding is not appropriate for high speed signal propagation between chips and causes several disadvantages such as limitation of the size reduction and deterioration of high frequency characteristics [1, 3]. As a new interconnection technology for 3D stacks packages, chip-to-chip vertical interconnection technology using vertical through vias has been proposed [8-10]. To apply through vias technology to 3D stacking package, electrical property of through vias should be characterized to estimate quality of the signal in 3D stacking package. In this study, 3D interconnection technologies for chip stack packages were reported. Also the contact resistance of a 3D interconnection joint was characterized with a chip-stack specimen of the daisy chain structure. An equivalent circuit model of a through via was proposed, which is fully composed of RLCG components.
EXPERIMENTAL PROCEDURE Via holes with 55 and 75um diameter, 170um depth, and 150um pitch were formed on 550um thick p-type (100) Si wafer which had resisitivity of 10Ω·cm by using deep RIE (Reactive Ion Etching). On surfaces of the silicon wafer and via holes, S
Data Loading...
