Fabrication of Strain Relaxed Silicon-Germanium-on-Insulator (Si 0.35 Ge 0.65 OI) Wafers using Cyclical Thermal Oxidatio
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0994-F09-03
Fabrication of Strain Relaxed Silicon-Germanium-on-Insulator (Si0.35Ge0.65OI) Wafers using Cyclical Thermal Oxidation and Annealing Grace Huiqi Wang1, Eng-Huat Toh1, Chih-Hang Tung2, Yong-Lim Foo3, S. Tripathy3, GuoQiang Lo2, Ganesh Samudra1, and Yee-Chia Yeo1 1 National University of Singapore, Singapore, 459441, Singapore 2 Institutue of Microelectronics, Singapaore, 117685, Singapore 3 Institute of Materials Research & Engineering, Singapaore, 117602, Singapore ABSTRACT A novel scheme for the fabrication of SiGe-on-insulator (SGOI) substrates comprising a thin and relaxed silicon-germanium (SiGe) layer with high Ge mole fraction is reported. A cyclical thermal oxidation and annealing (CTOA) process is introduced to alleviate issues associated with surface roughening and non-uniformity in Ge content. A systematic study of the stress developed in the SiGe layer as condensation takes place is presented. A clear understanding of the strain evolution enables the SGOI substrate fabrication to be tailored according to the requirements of strain engineering in high mobility MOSFETs. INTRODUCTION Group-IV high-mobility semiconductors such as Ge [1] and SiGe [2] has been considered as alternative channel materials for further extension of MOSFET performance. Channel materials with higher carrier mobilities than Si achieves a higher drive current for a given power supply voltage. SiGe-on-insulator (SGOI) or Ge-on-insulator (GOI) substrates also provide better electrostatic control and reduced short channel effects, especially when the semiconductor thickness is scaled into the ultra-thin regime. High quality SGOI substrates are desired. Substrates with high defect density and a rough surface would degrade transistor drive current and gate oxide quality. In addition, Ge has a lattice constant that is similar to that of gallium arsenide (GaAs), and could enable the integration of GaAs-based devices on Group-IV semiconductor substrates. One method of forming SGOI or GOI substrates employs the Ge condensation process. The quality of the SGOI or GOI substrate formed depends on the choice of the initial substrate parameters (SOI thickness, SiGe thickness, Ge content etc.), and the process conditions during the Ge condensation process. In this work, we adopt a novel condensation technique and report the physics and formation of high quality thin-body silicon-germanium-on-insulator (SGOI) substrates. This technique is promising for the fabrication of dislocation-free SGOI layers for thin-body transistors. The fabrication of a partially relaxed Si0.35Ge0.65OI which is applicable to strained MOSFET applications is also presented. The key mechanisms for increasing the Ge fraction, and relaxing the SiGe layer without the generation of dislocations are discussed.
Si Layer Si1- xiGe xi Layer
Surface Oxide
xi :0.137
xi :0.133 xi :0.142 xi :0.138
xi :0.140 xi :0.134 xi :0.136
SiGe Layer
xi :0.136
Si Layer
xi :0.007 xi :0.000
xi :0.007 xi :0.000
Buried Oxide (BOX)
Si substrate
Buried Oxide (BOX)
20nm
Figure 1. S
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