• PDF / 545,922 Bytes
• 4 Pages / 612 x 792 pts (letter) Page_size
• 99 Downloads / 201 Views

DOWNLOAD

REPORT

---

Flash Memory Scaling Al Fazio Abstract In order to meet technology scaling in the field of solid-state memory and data storage, the mainstream transistor-based flash technologies will start evolving to incorporate material and structural innovations. Dielectric scaling in nonvolatile memories is approaching the point where new approaches will be required to meet the scaling requirements while simultaneously meeting the reliability and performance requirements of future products. High-dielectric-constant materials are being explored as possible candidates to replace the traditional SiO2 and ONO (oxide/nitride/oxide) films used today in memory cells. Likewise, planar-based memory cell scaling is approaching the point where scaling constraints force exploration of new materials and nonplanar, three-dimensional scaling alternatives. This article will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor floating-gate-based nonvolatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor-based flash memory cells can scale through at least the end of the decade (2010) using techniques that are available today or projected to be available in the near future. More complex, structural innovations will be required to achieve further scaling. Keywords: flash memory, floating gates, nonvolatile memory, scaling.

drain, transistor channel, and polysilicon control gate terminals. Any charge present on the floating gate is retained due to the inherent Si-SiO2 energy barrier height, leading to the nonvolatile nature of the memory cell. Characteristic of the structure is a thin tunneling oxide (
100 Å), an oxide/nitride/oxide (ONO) interpoly dielectric (IPD) that resides between the two polysilicon gates, and a short electrical channel length. Because the only electrical connection to the floating gate is through capacitors, the flash cell can be thought of as a linear capacitor network with an n-channel transistor attached. The threshold voltage of the device can be changed by modifying the charge on the floating gate, which can retain this charge for many years. Data can be stored in the memory by adding or removing charge. In the simplest form of a memory cell, two threshold levels (high and low) can store one bit of information in each cell. This concept can be extended to store more levels, commonly called an MLC (multilevel cell).3 Four levels would allow two bits of data per cell to be stored. Adding and removing charge from the floating gate is normally achieved by Fowler–Nordheim tunneling or hot carrier injection.

Flash Cell Programming Introduction Floating gate flash memory1,2 is now the fastest-growing memory segment, driven by the rapid growth of portable devices such as digital cameras and cellular phones. The technology allows for data stored in multiple memory cells to be erased in a single action (a “flash”) by means of an applied voltage. Flash memory is categorized into two basic approaches: