Scaling Challenges for NAND and Replacement Memory Technology
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Scaling Challenges for NAND and Replacement Memory Technology Kirk Prall Micron Technology, 8000 S. Federal Way, Boise, ID 83716 [email protected] ABSTRACT Planar NAND technology is rapidly approaching its fundamental limits and will likely transition to a three dimensional structure. The scaling challenges facing NAND will be reviewed. Emerging memory technologies, such as the cross-point, will be discussed. The materials challenges facing emerging memories will be reviewed. INTRODUCTION NAND is currently the dominant semiconductor non-volatile storage technology used in solid state discs, USB flash cards, camera cards, etc. NAND technology has been rapidly scaling, faithfully following Moore’s law since its invention circa 1987 by Toshiba [25]. NAND is facing severe scaling challenges which will likely result in the end of planar silicon scaling at around the 15nm generation. NAND may survive by adopting a 3-D structure, continuing to increase density, and reducing cost by adding layers in the third dimension. A possible alternative path may be that NAND will be replaced by a technology operating on a new mechanism that departs from silicon based electron storage. Large materials challenges exist and major breakthroughs will be required to successfully commercialize a NAND successor. NAND SCALING Currently, NAND manufacturers are shipping high volumes of product in the 20-25nm range [1][26]. There is a large research effort to push planar NAND technology to its ultimate limit. The amount of money expended on NAND research and development yearly is in the range of $750M-$1B; giving the technology a huge amount of technical momentum and enabling NAND to outrun other potential technologies. The technical challenges facing NAND are daunting and will ultimately lead to the demise of planar NAND as we know it. The technical challenges facing NAND scaling are summarized in Table I. There are several categories to consider: fundamental capacitance limits caused by scaling, scaling issues caused by the inability to reduce voltages or dielectric thickness, and reliability challenges.
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Table I NAND Scaling Challenges
Ref #
Capacitance Issues Floating gate capacitance trending to zero Electrons per cell trending to zero Interference (parasitic capacitance trending to 100%)
[1][2] [1][2] [3][4][5]
Scaling Issues Tunnel oxide thickness stuck at ~7nm Interpoly dielectric thickness stuck at ~10nm Cell operating voltages stuck at ~25V (MLC) Isolation stuck at ~6-8V, high aspect ratio isolation Inhibit stuck at ~10V Wordline to Wordline field trending to >10 MV/cm Variation increasing Noise increasing Quantum mechanical tunneling noise Parasitic electron trapping
[6] [7] [1][2] [1][2] [8] [1] [9][10][11] [12][13] [14] [1]
Reliability Challenges Program disturb Trapping / detrapping Quick electron detrapping Stress induced related charge loss Retention is degrading Read disturb Cycling is degrading Random telegraph signal noise Increasing ECC requirements
[15][16] [17] [18] [6] [19],[20] [21] [22] [23] [1][24]
Several of
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