Overview of Advanced 3D Charge-trapping Flash Memory Devices (Invited)

  • PDF / 894,314 Bytes
  • 6 Pages / 612 x 792 pts (letter) Page_size
  • 103 Downloads / 232 Views




OVERVIEW OF ADVANCED 3D CHARGE-TRAPPING FLASH MEMORY DEVICES (INVITED) Hang-Ting Lue, Kuang-Yeu Hsieh, and Chih-Yuan Lu Macronix International Co., Ltd., 16 Li-Hsin Road, Hsinchu 300, Taiwan, R.O.C. e-mail: [email protected]

ABSTRACT Although conventional floating gate (FG) Flash memory has already gone into the sub-30 nm node, the technology challenges are formidable beyond 20nm. The fundamental challenges include FG interference, few-electron storage caused statistical fluctuation, poor short-channel effect, WL-WL breakdown, poor reliability, and edge effect sensitivity. Although chargetrapping (CT) devices have been proposed very early and studied for many years, these devices have not prevailed over FG Flash in the > 30nm node. However, beyond 20nm the advantage of CT devices may become more significant. Especially, due to the simpler structure and no need for charge storage isolation, CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the Moore’s law to continue for at least another decade. In this paper, we review the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss 3D memory architectures including the bit-cost scalable approach. Technology challenges and the poly-silicon thin film transistor (TFT) issues will be addressed in detail. Introduction Charge-Trapping (CT) NAND Flash Figure 1 briefly compares the FG and CT NAND. CT NAND has several advantages over FG: It can be integrated in a simpler planar structure, and the discrete trap charge storage can suppress interference and stress induced leakage current (SILC) issues. For 3D memory, it is not necessary to cut through the ONO charge-trapping layer, and this greatly simplifies the 3D memory process and enables the ultra low cost memory. Figure 2 illustrates several examples in previous works [1-3].

Fig. 1 Comparison of FG NAND and CT NAND.

Fig. 2 Several examples of 3D CT NAND Flash devices. [1-3]

Fig. 3 Comparison of FG NAND and CT NAND.

Fig. 4 FinFET BE-SONOS and Field enhancement effect.

Figure 3 briefly illustrates several important candidates for charge-trapping devices [4-8]. The conventional SONOS/MONOS can not find a suitable operation window due to the difficult trade off between the erase and retention. Two approaches were extensively proposed. The first one is to use high-K top dielectric and a high work function metal gate (MANOS) to suppress the gate injection and erase saturation [6]. However, the erase speed is still very slow because the major erase mechanism comes from electron de-trapping out of nitride. To expel the deeply trapped electrons out of nitride is very inefficient, and it shows a gradually slower erase speed due to the electron trapped energy “spectrum blue shift” [9]. Moreover, the very high field

during erase also damages the tunnel oxide reliability. To further improve the electron detrapping speed one must detune the nitride to a “shallowly trapping” material such as silicon-rich nitrid