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1079-N02-01

From Process Assumptions to Development to Manufacturing Theo Standaert1, Allen Gabor1, Andrew Simon1, Anthony Lisi1, Carsten Peters2, Craig Child2, Dimitri Kioussis2, Edward Engbrecht1, Fen Chen1, Frieder Baumann1, Gerhard Lembach2, Hermann Wendt2, Jihong Choi2, Joseph Linville2, Kaushik Chanda1, Kaushik Kumar1, Kenneth Davis1, Laertis Economikos1, Lee Nicholson1, Moosung Chae3, Naftali Lustig1, Oscar Bravo1, Paul McLaughlin1, Ravi Prakash Srivastava4, Ronald Filippi1, Sujatha Sankaran1, Tibor Bolom2, Vinayan Menon1, Vincent McGahay1, Wai-Kin Li1, Wei-Tsu Tseng1, William Landers1, Youngjin Choi1, Glenn Biery1, and Thom Gow1 1 IBM, Hopewell Junction, NY, 12533 2 AMD, Hopewell Junction, NY, 12533 3 Infineon, Hopewell Junction, NY, 12533 4 Chartered, Hopewell Junction, NY, 12533 ABSTRACT A tool has been developed that can be used to characterize or validate a BEOL interconnect technology. It connects various process assumptions directly to electrical parameters including resistance. The resistance of narrow copper lines is becoming a challenging parameter, not only in terms of controlling its value but also understanding the underlying mechanisms. The resistance was measured for 45nm-node interconnects and compared to the theory of electron scattering. This work will demonstrate how valuable it is to directly link the electrical models to the physical on-wafer dimensions and in turn to the process assumptions. For example, one can generate a tolerance pareto for physical and or electrical parameters that immediately identifies those process sectors that have the largest contribution to the overall tolerance. It also can be used to easily generate resistance versus capacitance plots which provide a good BEOL performance gauge. Several examples for 45nm BEOL will be given to demonstrate the value of these tools. INTRODUCTION When a new technology node gets introduced to its development phase there is typically little or no silicon data. In this concept stage most of the technology definition and elements are therefore based on assumptions. One considers the learning from prior technologies as well as new material and process candidates that are presented by the research community. The result is a set of assumptions that best describes what is expected to happen on wafer for each of the processing steps. This set is commonly referred to as the process assumptions. As real silicon data becomes available it can be used to update and refine the process assumptions. This work describes how to set up the process assumptions and directly link it to electrical models. The result is a valuable tool that can be used to evaluate various BEOL options and to validate a BEOL technology.

SETTING UP BEOL PROCESS ASSUMPTIONS Capturing processing details Each processing step on the wafer can be captured by a schematic and a simple set of equations. Figure 1 shows an example for metal 1 where the contact module is followed by a dielectric deposition, lithography and etch.

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Figure 1: Schematic of how metal 1