From SOI 1T-DRAMs to Unified Memory Concepts
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From SOI 1T-DRAMs to Unified Memory Concepts Sorin Cristoloveanu1 and Maryline Bawedin2 1 IMEP-LAHC (UMR 5130), Grenoble INP Minatec, 38016 Grenoble Cedex 1, France 2 IES (UMR 5214), Université de Montpellier II, 34095 Montpellier, France ABSTRACT The typical architectures for single-transistor capacitorless dynamic random access memory (1T-DRAM) are reviewed. This memory takes advantage of floating-body effects in SOI-like devices. The principles of operation and the key mechanisms for memory programming and reading are described. Most of these devices can be enriched with non-volatile storage capability. Several possibilities for such ‘unified’ memory are explored. INTRODUCTION Since the scaling of the DRAM storage capacitor is a nightmare, a responsible strategy consists in simply suppressing it. The Silicon-on-Insulator (SOI) technology offers the possibility to store the charges directly in the floating body of a MOSFET which is also used to read the data. These memories, usually referred to as 1T-DRAMs, use only one transistor and take advantage of floating-body effects that were considered before as parasitic phenomena. In the last decade, many 1T-DRAM versions have been conceived: partially (PD) or fully depleted (FD), simple-gate or double-gate, planar or vertical (FinFET), etc. We will review the most promising concepts, by focusing on MSDRAM, ARAM, and Z2-RAM. The device geometry, scaling issues and different methods for programming and reading will be discussed. An even more advanced paradigm is the ’unified’ memory device. An ideal candidate is again the SOI MOSFET which basically features two (or more) independent gates: each gate can be given separate tasks (program, store or read the charge). We will show solutions for (i) combining, within a single SOI transistor, volatile and nonvolatile memory functionalities, and (ii) reaching multiple memory states. 1T-DRAM PRINCIPLES The isolated body (Fig. 1) of the SOI transistors provides an ideal storage volume. The 1T-DRAMs take advantage of floating-body effects and coupling mechanisms that are often viewed as annoying effects. In all 1T-DRAM variants, state ‘1’ (high drain current) reflects an excess of majority carriers in the body which increases the potential and hence the drain current. Conversely, state ‘0’ features a lower current due to the removal of majority carriers from the body (Fig. 1). PD SOI 1T-DRAMs are single-gate operated, i.e. with grounded back gate (VGB = 0), and the excess carriers can be stored in the neutral region of the body (Fig. 1a,b). In FD SOI, there is no neutral region and back-gate biasing is required to accommodate the majority carriers in the back accumulation layer (negative VGB in Fig.1). The electrostatic coupling between the front and back interfaces is used to sense the drain current during the reading. The front inversion current reflects the state of the back channel: depletion or accumulation. 1T-DRAMs can be differentiated according to the mechanism used to generate the majority carriers.
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Fig. 1 Schematic
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