Gate Stacks for Low Voltage Ferroelectric Field Effect Devices Based on Pt/SBT/CeO 2 /Si(100)
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ABSTRACT METS (Metal Ferroelectric Insulator Semiconductor) capacitors were fabricated using CSD (Chemical Solution Deposition). Thin layers of CeO 2 were deposited as an insulating buffer layer on Si(100) substrates and SrBi 2Ta 2O9 (SBT) was used as a ferroelectric layer. Pt electrodes were deposited by evaporation on top of the SBT layer. At constant SBT thickness the thickness of the CeO2 layer was varied to investigate the effects of the change in capacitance ratio between the ferroelectric and the buffer layer. XRD spectra were used to determine the phase of the SBT and the quality of the CeO 2 layer. C(V) measurements showed the ferroelectric nature of the SBT. Additional information was provided by TEM and EDX analysis. Some samples showed a memory window as big as 1.6 Volt at a moderate voltage sweep from -3.5 to +3.5 Volt. Interface state density is approximately 2xl0'I/cm2 eV and remanent polarization was found to be in the range of 0.3 pC/cm 2. These results are already very promising in terms of fabricating a Ferroelectric FET. Some basic considerations with respect to the development of iT memory cells on the basis of this kind of transistor will also be presented. INTRODUCTION Ferroelectric field effect devices provide the possibility to fabricate unique memory devices combining characteristics such as high speed, non-volatility, and high density. They have the potential to replace state of the art nonvolatile memories [1,2]. However, two major challenges are still ahead on the way to a 1 transistor memory cell. Both cell architectures presented so far [3], as well as devices themselves [4], need further improvement. We are currently investigating the feasibility of ferroelectric devices capable of low voltage operation, which is one of the prerequisites for their integration [5]. Memory cells based on a ferroelectric FET can only replace Flash and EEPROM devices if they can be operated at low voltages. To reduce the operating voltage of such devices, the capacitance ratio between the buffer layer and the ferroelectric layer must be optimized. This can be achieved by choosing materials with appropriate dielectric constants [6] and by adjusting the thickness of the layers [7]. EXPERIMENTAL Processing of the Si(100) wafers started with a 1 minute HF dip, a subsequent 10 min DI water rinse, and drying. CSD was used to deposit thin layers of Ce solution onto the cleaned wafers. Spin on was done within 20 minutes after the cleaning at 4000 rpm. Thickness was adjusted between 7 and 21 nm by varying the concentration of the Ce solution between 0.067 and 0.1 3M. N-butyl acetate was added for dilution. The as deposited layer was dried for 1 minute at 160'C and for 4 minutes at 260'C on appropriate hot plates. After that the samples were 437 Mat. Res. Soc. Symp. Proc. Vol. 596 ©2000 Materials Research Society
annealed at 700'C in oxygen for one hour. To generate a 180 nm thick SBT layer two spin on steps were done subsequently each at 1800 rpm. Each of these steps was followed by a 30 second anneal in oxygen
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