Gold Langmuir-Blodgett deposited nanoparticles for non-volatile memories
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Gold Langmuir-Blodgett deposited nanoparticles for non-volatile memories
S. Kolliopoulou1, D. Tsoukalas2, P. Dimitrakis1 and P. Normand1 S. Paul3, C. Pearson3, A. Molloy3, M. C. Petty3 1 Institute of Microelectronics, NCSR Demokritos, 153 10 Aghia Paraskevi, Greece 2 National Technical University of Athens, 15780 Zografou, Greece 3 Centre for Molecular and Nanoscale Electronics, University of Durham, Durham DH1 3LE, UK ABSTRACT In this work, we demonstrate a MISFET memory device that incorporates a monolayer of Langmuir-Blodgett (LB) deposited gold nanoparticles as floating gate charge storage elements. The FET device is fabricated on a SOI substrate using conventional silicon processing. The nanoparticle layer is separated from the channel area of the FET with a 5 nm thermal SiO2 layer and is isolated from Al gate contact with a LB-deposited organic insulator layer. The memory effect is tested using voltage pulses on the gate of the device and monitored through drain current measurements. The nanocrystals can be charged either from the channel through the thermal oxide layer by applying pulses smaller than 5 V or from the gate through the organic insulator for higher voltage depending on the pulse duration. INTRODUCTION Metallic or semiconducting nanoparticles are under investigation as charge storage elements to replace the continuous polysilicon layer of EEPROM devices. One challenging aspect remains the method of formation of the nanoparticles and its integration with silicon technology. Major efforts have been concentrated towards the demonstration of CMOS compatible high temperature techniques for nanoparticle formation and subsequent memory device operation [1-3]. In this work we attempt to combine room temperature gold nanoparticle deposition and its use for a memory device demonstration. Along these lines a silicon FET was used in a similar to EEPROM device architecture in order to probe the charge storage properties of the gold nanoparticles. Room temperature formation of nanoparticles might be considered as a critical step towards the fabrication of a low processing temperature memory device. The low temperature concept could find application in future 3-D memory architectures combined either with silicon or more probably with other low temperature processed materials like polymers. It should be noted that gold nanoparticles, deposited at room temperature, have been already used on top of GaAs substrates and electronic coupling to the substrate observed [4]. Furthermore, Sato and Ahmed [5] have used colloidal gold nanoparticles between two closely spaced metal electrodes and have observed Coulomb blockade phenomena at low temperatures. EXPERIMENTAL DETAILS A commercially available p-type SIMOX wafer with silicon over-layer thickness of 200 nm and a buried oxide thickness of 400 nm was used as the starting material. The first fabrication process step consists of the growth of 10 nm thick sacrificial dry oxide and the
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removal of the silicon over-layer except from the areas used for device
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