High Quality Poly-Si Film and Transistor Formed by Nickel-Induced- Lateral-Crystallization and Pulsed-Rapid-Thermal-Anne
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High Quality Poly-Si Film And Transistor Formed By Nickel-InducedLateral-Crystallization And Pulsed-Rapid-Thermal-Annealing
T.C. Leung, C.F. Cheng, M.C. Poon, Dept. of Electrical and Electronic Engineering, Hong Kong University of Science & Technology, Sai Kung, Hong Kong
ABSTRACT Nickel Induced Lateral Crystallization (NILC) and Pulsed Rapid Thermal Annealing (PRTA) have been used to study new low temperature and high quality poly-silicon (poly-Si) films and thin film transistors (TFTs). The growth rate of poly-Si films has been found to greatly increase from 0.025µm/minute to 1.07µm/minute, and the drain current and performance of TFTs have increased by around 75%. The new poly-Si technology has good potential to apply in high performance, large area, fast throughput, low cost and even low temperature device applications.
INTRODUCTION High quality poly-silicon (poly-Si) film can have numerous applications in novel devices and Large Area Electronics (LAE). Recently, Nickel-Induced-Lateral-Crystallization (NILC) of amorphous-Si (a-Si) has successfully achieved large grain (micron size) poly-Si film and SOI like thin-film-transistor (TFT) [1-5]. However the poly-Si growth rate is slow (0.025µm/minute at 550 o C) and annealing time is usually very long (> 30 hours). This work presents a new technology to combine NILC and Pulsed Rapid Thermal Annealing (PRTA) to shorten the anneal time and to obtain high quality (and even low temperature) poly-Si films and TFTs.
EXPERIMENTAL 4000Å of thermal oxide was grown on (100) silicon wafers. 1000Å of a-Si was deposited on the oxide by low-pressure chemical vapor deposition (LPCVD) at 550oC, followed by the deposition of 4000Å of low temperature oxide (LTO) at 425oC. Windows were then opened on the LTO. Native oxide on the a-Si was removed by dilute HF dip. 50Å nickel was deposited by D3.4.1
electron beam evaporation. The wafers were then annealed using the PRTA and conventional constant temperature furnace annealing respectively to perform lateral crystallization in pure N2 ambient. The films after 700 oC PRTA and 550oC constant temperature annealing were used as the substrates to fabricate NMOS transistors. Nickel and oxide on the wafer surface were removed by H2SO4 and BOE solution respectively. The channel implant was BF2 with dose 5x1012/cm2 at 60keV. The active area island was then defined by patterning the lateral crystallization region. 300Å of LTO was deposited as gate oxide. 3000Å of poly-Si was then deposited by LPCVD at 620oC to act as the gate silicon. After gate patterning and etching, source and drain doping was performed by implanting phosphorus with dose 5x1015/cm2 at 50keV. After that, 4000Å of LTO was deposited by LPCVD. Some wafers were then put into the furnace to anneal at 900oC for 1hr in N2 ambient while some wafers were annealed at 600oC for 20hours in N2. Contact holes were opened and 7000Å of aluminum was deposited by sputtering. Aluminum patterning was performed and finally followed by the sintering at 400oC for 30 minutes in forming gas. TFTs wi
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