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TRANSIENT AND STRESS EFFECTS IN AMORPHOUS SILICON THIN-FILM TRANSISTORS

M. HACK, R. WEISFIELD, *M.F. WILLUMS, *G. H. MASTERTON and *P. G. LeCOMBER Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304 *University of Dundee, Dundee DD1 4HN, Scotland

ABSTRACT In this paper we present experimental and simulation results of the transient response of amorphous silicon (a-Si) thin film transistors (TFTs) over many orders of magnitude in time after the application of a voltage pulse to the gate. In general three regimes are observed by plotting drain current versus the logarithm of time. At times longer than the carrier transit time and extending up to 1 - 100 msecs, the current rapidly decreases due to trap filling, after which it then slowly decays up until defects are created in the silicon channel when it then finally decays more rapidly again. Our simulation results are in good agreement with the data for the short time trap filling regime, as a function of both gate bias and stress condition. Measurements at elevated temperatures show that the middle slow decay regime is caused by charge injection into interface states or the gate dielectric. Finally we also demonstrate that this slow decay regime does not occur in nin diodes, confirming that it is not caused by defect generation in the a-Si, and is instead related to the presence of the dielectric in a TFT. INTRODUCTION Thin film transistors (TFTs) have now become an essential component of high performance large area imaging and liquid crystal display (LCD) arrays. In these applications it is important to understand the transient response of the TFT current - voltage characteristics. These were first reported by van Berkel et al and Powell [1,21 who considered the dynamic behaviour of the drain current of an a-Si TFT upon application of a gate voltage. They show three basic regimes. Between 1 ps and ils they observe transient effects attributed to carrier trapping in the a-Si, a region between 1 and 100 s where the current is independent of time, and beyond 100 s a third regime where the current decreases due to defect creation in the a-Si. All this work was performed on samples with a silicon thickness dsi of 0.30pm. In earlier work [3] we repeated these measurements on our samples having dsi = 0.06pm, more typical of devices used in large area applications. We found, as expected, that the carrier trapping effects reach their steady-state value at shorter times in thinner devices. Moreover, we were also able to obtain good fits between the experimental data of the current transients approximately 1 psec to 1 msec after the application of a gate pulse, and the results of a two-dimensional computer simulation for a-Si TFTs [4]. This enabled us to obtain information as to the capture rates of traps in the upper half of the a-Si bandgap. [3]. However, experimentally we observed a slow decrease in current continuing in time beyond 1 msec until the onset of the defect creation regime, previously observed starting at 10 - 100 seconds. This feature