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High Yield Polymer MEMS Process for CMOS/MEMS Integration Prasenjit Ray, V. Seena, Prakash R. Apte, Ramgopal Rao Centre of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India.

ABSTRACT MEMS community is increasingly using SU-8 as a structural material because it is selfpatternable, compliant and needs a low thermal budget. While the exposed layers act as the structural layers, the unexposed SU-8 layers can act as the sacrificial layers, thus making it similar to a surface micromachining process. A sequence of exposed and unexposed SU-8 layers should lead to the development of a SU-8 based MEMS chip integrated with a pre-processed CMOS wafer. A process consisting of optical lithography to obtain SU-8 structures on a CMOS wafer is described in this paper. INTRODUCTION The negative photoresist SU8 has been in use for developing high aspect ratio Microelectromechanical system (MEMS) structures. SU8 structures with aspect ratio up to 25 have been reported[1-5]. Such high aspect ratio structures are used to fabricate devices like cantilevers, accelerometers, pressure sensors, micromirrors etc. Due to the low process temperature of SU8, it is possible to follow the monolithic approach of “CMOS first MEMS last” for realization of System-On-Chip (SOC) applications. One of the processes for fabrication of suspended SU8 structures is the flip-chip release technique [6-7]. Other technique to get hanging SU8 structure on the wafer is to use e-beam lithography with varying exposure energy [8]. One of the more successful methods is the use of Al film between SU8 layer to stop UV light propagation to the sacrificial SU8 layer [9,10]. Some investigators have used Microstreolithography [11], antireflection coating to control the dose[12], and a proton beam [13] to get the complex structures in SU8. A somewhat complex process called the planar selfsacrificial multilayer SU-8 (PSALMS) allows fabrication of hinges and rotating parts in SU8.[14]. In this paper a process flow to fabricate suspended structures on the substrate using a standard optical lithography is described. A novel concept of including an embedded mask of SU8/Carbon Black has been used to prevent exposure of the sacrificial SU-8 layer. This process has a very high yield and it can be used as a post CMOS process step to fabricate complex SU8 structures for realization of CMOS-MEMS. EXPERIMENTAL DETAILS SU8/Carbon black composite is used as an embedded mask to protect the lower layer of SU8 from getting exposed so as to allow fabrication of complex structures of SU8. Sacrificial layers of unexposed SU8 are removed in one single SU-8 developing step at the end of the entire

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process. In this paper a process for obtaining only two layer structures has been shown but it is possible to fabricate more than two layer SU8 structures using multiple uses of these process steps. Processing Steps Process steps for fabricating a suspended structure on silicon wafer are given below,

Figure 1. Process Steps fo