Impact of trap charge and temperature on DC and Analog/RF performances of hetero structure overlapped PNPN tunnel FET
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Impact of trap charge and temperature on DC and Analog/RF performances of hetero structure overlapped PNPN tunnel FET Karabi Baruah1 · Rajashree Das1 · Srimanta Baishya1 Received: 19 December 2019 / Accepted: 4 October 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract Impact of interface trap charges (ITCs) as well as temperature on the performance of a proposed dual dielectric constant spacer source/drain, overlapped double gate tunnel FET with a source pocket was investigated using two-dimensional Technology Computer-Aided Design (TCAD) device simulator. The proposed device is Si-based with Germanium as the source material, SiGe as a pocket material, and has a high-k gate dielectric. Its performance in terms of DC and analog/ RF parameters vis-à-vis a conventional double gate PNPN TFET was compared. The device shows better results than the conventional one with an ON current of 1.71 × 10−3 A/µm, ON–OFF current ratio 1011, and subthreshold swing of 45 mV/ decade. The study was focused on the analysis of the electric field, transfer characteristics, transconductance (gm), output conductance (gd), parasitic capacitances, gain-bandwidth product (GBP), cut off frequency (fT) for both the damaged (presence of donor/acceptor interface trap charges) and undamaged (no trap) conditions. The study revealed that the proposed structure is more immune to the interfacial trap charges as compared to the conventional device. Apart from this, the analysis shows a degradation of subthreshold swing (SS) and OFF current (IOFF) at elevated temperatures. Keywords Band to band tunneling (BTBT) · Cut off frequency (fT) · Dual-k spacer · DG-TFET · Gain-bandwidth product (GBP) · Source and drain overlap · Temperature sensitivity (sT) · Tunnel field-effect transistor (TFET)
1 Introduction Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have played a vital role in the exponential growth of the microelectronics industry. However, aggressive downscaling of the same gives rise to several serious issues such as high leakage current, high subthreshold swing, and other short channel effects which degrade the device performance for low power applications [1, 2]. These challenges enforce the researchers to look for new devices whose operation mechanism may be different from that of MOSFET i.e. the thermionic emission. In this regard, Tunnel FET can be considered as a fit candidate for low power applications in advanced technology node. It can overcome the fundamental limit of subthreshold swing (60 mV/decade) of conventional MOSFET using interband tunneling at the source-channel * Karabi Baruah [email protected] 1
Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Silchar, Assam, India
junction [3, 4]. In the case of n-channel TFET, the source is p-type and tunneling of electrons occurs from the valence band of the source to the conduction band of the channel. This interband tunneling mechanism allows TFET to exhibit low subthreshold swing a
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