Impact of Temporal Variability on Dopingless and Junctionless FET based SRAM Cells
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ORIGINAL PAPER
Impact of Temporal Variability on Dopingless and Junctionless FET based SRAM Cells Meena Panchore1
· Kanchan Cecil2 · Jawar Singh3
Received: 10 May 2020 / Accepted: 29 September 2020 © Springer Nature B.V. 2020
Abstract In this brief, we have explored the impact of negative and positive bias temperature instability (NBTI and PBTI) for both DL (dopingless) and conventional junctionless (JL) FET based SRAM cells under worst-case scenario (extreme asymmetry). Using device-circuit co-simulation approach, read stability and delay of high performance and high density SRAM cells have been investigated for temporal variability due to NBTI+PBTI and NBTI (alone) of time span 2000s. The read static noise margin of high density SRAM cell based on DL-JLFET has 11% reduction as compared to 33% for conventional JLFET under NBTI+PBTI. It is observed that the DL-JLFET experiences less and symmetric shift in VT H compared to conventional JLFET under NBTI and PBTI, hence, circuits based on DL-JLFET may be less sensitive to temporal variations. Keywords Conventional JLFET · Dopingless (DL)-JLFET · NBTI · PBTI
1 Introduction Junctionless field effect transistors (JLFETs) [1] have gained substantial attention in the recent past due to their better electrostatic integrity and inherent ability to mitigate the short channel effects (SCEs). However, process variability [2] with scaled device dimensions is still a major concern in JLFETs. Higher body doping induced random dopant fluctuation (RDF) [3] in JLFET exacerbates the switching ability, hence, end applications are susceptible to process variations. The time dependent performance degradation in n-channel JLFET due to channel hot carrier (CHC) Meena Panchore
[email protected] Kanchan Cecil [email protected] Jawar Singh [email protected] 1
Department of Electronics and Communication Engineering, National Institute of Technology, Patna, 800005, India
2
Department of Electronics and Telecommunication Engineering, Jabalpur Engineering College, Jabalpur, 482011, India
3
Department of Electrical Engineering, Indian Institute of Technology Patna, 801106, India
stress was experimentally found less in contrast to its counterpart inversion mode MOSFETs [4, 5]. In addition, p-channel JLFETs have also been investigated for negativebias temperature instability (NBTI) [6, 7] with less time dependent performance degradations provided that other sources of variability are suppressed. However, higher body doping an essential pre-requisite in JLFETs for matching the driving current may yield significant temporal variability due to negative/positive bias temperature instability (NBTI/PBTI) [8]. Higher body doping in JLFETs for high carrier concentration in source to meet the driving current requirement exaggerates variability. Therefore, a lowly doped (or dopingless) channel JLFET, referred as dopingless (DL) JLFET has recently been introduced as a potential candidate to address the process variation induced RDFs, while preserving all the inherent benefits of JLFET [2,
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