Investigation of Hetero Buried Oxide and Gate Dielectric PNPN Tunnel Field Effect Transistors
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ORIGINAL PAPER
Investigation of Hetero Buried Oxide and Gate Dielectric PNPN Tunnel Field Effect Transistors K. Ramkumar 1 & V. N. Ramakrishnan 1 Received: 24 May 2020 / Accepted: 15 September 2020 # Springer Nature B.V. 2020
Abstract This paper investigates a novel hetero dielectric buried oxide and gate dielectric based PNPN tunnel field effect transistor (HDBHDG-PNPN-TFET) using 2-D simulation. The buried oxide (BOX) is formed by SiO2 below the channel and source, HfO2 beneath the drain region. The asymmetrical gate oxide is formed by high-k and low-k dielectric material on the source and drain side respectively. The asymmetrical gate oxide decreases the tunneling width at the drain-channel (JDC) and source-channel (JSC) junctions and improves ON-current (ION). The buried oxide above the degenerated P+ substrate determines the tunneling width at the JDC and minimizes the ambipolar current. The device simulations show a low OFF-current (IOFF) of 4.21× 10−17 A/μm, a greater ION of 4.12× 10−4 A/μm, average and point subthreshold swing (SS) of 29.12 mV/dec and 19.38 mV/dec respectively for HfO2− SiO2 gate oxide. The above-mentioned result enables the device to be opted for low power applications. Keywords Ambipolarity . Band-to-band tunneling (BTBT) . High-k dielectric . MOSFETs . Tunnel FETs (TFETs)
1 Introduction Ever since the invention of field effect transistors (FETs) and Complementary Metal Oxide Semiconductor (CMOS) technology, both architecture of the device and fabrication process have undergone numerous changes but the device fundamentals have not changed. In metal oxide semiconductor FETs (MOSFETs), current transport mechanism is due to the surmounting of carriers over a potential barrier [1–4] and the subthreshold slope is limited to 60 mV/dec [5]. The device dimensions of MOSFETs are scaled down in order to achieve higher packing density, reduction in delay and consumption of power. However, limitations of device dimensions, subthreshold swing and short channel effects did not allow the scaling law to continue. In advanced technology nodes, keeping the power consumption within a reasonable limit becomes a bottleneck. Hence, we require steep subthreshold slope devices like tunnel FET for energy efficient and low-power applications [6–12]. In brief, a P-I-N structure device operated under reverse biased condition forms a TFET. In TFETs, carrier * V. N. Ramakrishnan [email protected] 1
School of Electronics Engineering, Vellore Institute of Technology, Vellore 632014, India
transport is due to band-to-band tunneling mechanism (BTBT), the device exhibits SS less than MOSFET and free from short channel effects (SCEs) [13, 14]. The applications of TFETs are limited due to ambipolar conduction and low ION. In order to reduce the ambipolar conduction, low drain doping, gate-drain underlaps, heterostructure with large bandgap materials at drain have been advised [15–22]. To increase the ION in TFETs gate, material and tunnel junction engineering have been proposed [23–31]. In gate engineering methods
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