Implementation of 12T and 14T SRAM Bitcell Using FinFET with Optimized Parameters
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Transactions on Electrical and Electronic Materials https://doi.org/10.1007/s42341-020-00243-7
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Implementation of 12T and 14T SRAM Bitcell Using FinFET with Optimized Parameters Rajesh Kumar Raushan1 · Mohammad Rashid Ansari1 · Usha Chauhan1 · Muhammad Khalid2 · Baibaswata Mohapatra1 Received: 28 May 2020 / Revised: 28 August 2020 / Accepted: 8 September 2020 © The Korean Institute of Electrical and Electronic Material Engineers 2020
Abstract In this paper, we have implemented 12T and 14T SRAM bitcell using FinFET with optimized parameters. Optimized parameters are related in terms average power consumption, delay, power delay product (PDP), and energy delay product (EDP). Simulation results of all parameters of 12T and 14T SRAM bitcell are reported with 22 nm FinFET technology. All parameters of 12T and 14T SRAM using FinFET are compared to conventional 12T and 14T SRAM and found that the results have improved in average power consumption, PDP, EDP, and propagation delay. Parameters for 12T SRAM using FinFET includes average power consumption, propagation delay, PDP and EDP, which are improved by 99%, 79.2%, 99.7% and 99.7%, respectively. Similarly, designing 14T SRAM using FinFET, gets improvements of 99% in Average Power consumption, 76.5% in propagation Delay, 99.4% in PDP, and 99.5% in EDP. Keywords SPICE · SRAM · Power · Delay · 22 nm · FinFET
1 Introduction Today many memories cells are available in the recent market such as flash memory (namely memristor) Dynamic Random-Access Memory (DRAM) and Static Random-Access Memory (SRAM) [1–3]. It plays a critical role in power, speed and performance in digital circuits, for example, the System-on-Chips (SoCs), microchips and microcontrollers all of these device performances depend on Random Access Memory (RAM). These memory clusters possess notable * Mohammad Rashid Ansari [email protected] Rajesh Kumar Raushan [email protected] Usha Chauhan [email protected] Muhammad Khalid [email protected] Baibaswata Mohapatra [email protected] 1
Department of ECE, SEECE, Galgotias University, Greater Noida, UP, India
Central Instrumentation Facility (CIF), Jamia Millia Islamia, New Delhi, India
2
portion of the chip area. Consequently, these memories cells (static RAM) as a general rule contribute for a higher division of the chip control. A few literary works have exhibited different designs for the SRAM cell, with their principle center around decrease of the cell territory, diminished gadget include and decrease in the discharge control. The IC design process to follow Moore’s law used optimization of layout metrics also meet the Moore’s law prediction the Network-on-Chip was proposed for many core systems for matching the processing speed with the memory with many routing algorithms among many core [4, 5]. However, as scaling of manufacturing nodes progressed within the direction of 22-nm, a number of the tool parameters couldn’t be scaled any additionally, specifically the threshold voltage, the dominant com
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