A Schmitt-trigger based low read power 12T SRAM cell
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A Schmitt-trigger based low read power 12T SRAM cell Ashish Sachdeva1
•
V. K. Tomar1
Received: 24 March 2020 / Revised: 9 September 2020 / Accepted: 18 September 2020 Ó Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract In this article, a Schmitt trigger based 12-Transistors(ST12T) static random-access memory (SRAM) bit-cell has been proposed. The Read Power of proposed cell is reduced by 29.17%/ 24.14% /7.66% /5.87% /7.67% /16.62% when compared to 6T/ 7T/ TA8T/ 9T/ PPN10T/ D2p11T SRAM cells. Proposed ST12T cell also shows 1.52 and 1.86 lesser variability in read current and read power respectively as compared to conventional 6T SRAM cell. Further, the write access time/read access time of the proposed topology are improved by 1:71 =1:82 as compared to 6T SRAM cell. The read power delay product of proposed ST12T cell is minimum with variation in supply voltage from 0.5 to 1 V when compared with all considered SRAM cells. ST12T SRAM cell also exhibits 26.82% and 8.87% higher read static noise margin and write static noise margin respectively as compared to conventional 6T SRAM cell. This may be attributed to Schmitt trigger design of inverters in core latch of proposed SRAM cell. The proposed bit-cell is free from half select issue and supports bit interleaving format. Authors have used cadence virtuoso tool with Generic Process Design Kit 45 nm technology file to carry out simulation. Keywords Read stability Low power Process variation Static random-access memory (SRAM) Write ability Half select
1 Introduction Improvement in integration density and device performance are logical outcomes of aggressive transistor scaling with each technology generation. The standby power reduction is crucial in battery operated devices such as portable medical equipment, IoT devices, cell phones etc. The effective solutions to control enhanced leakage power is reduction in supply voltage or improvement in circuit level techniques. Minimizing supply voltage is a tested and effective measure as it declines dynamic power in quadratic manner [1]. Therefore, supply voltage scaling becomes a major focus in low power design. However, with the reduction in supply voltage, the increase in sensitivity of various parameters of circuit to process
& Ashish Sachdeva [email protected] V. K. Tomar [email protected] 1
Department of Electronics and communication Engineering, GLA University, Mathura, India
variations is also observed [2]. The circuit operation is also limited by process variations, specifically in memory topologies, where many similar circuits are interconnected to execute required operation [3]. In a system-on-chip (SOC) device, embedded memories are expected to occupy 80–85% of total die area [4]. Intra-die variations in nanoscaled SRAM bit-cells include line edge roughness (LER), random dopant fluctuations (RDF) etc. These variations may result in threshold voltage mismatch between end- toend placed transistors in embedded memory [5].Furthermore, many techniques such as dy
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