Improved Deep Trench Super-junction LDMOS Breakdown Voltage By Shielded Silicon-Insulator-Silicon Capacitor
- PDF / 1,793,055 Bytes
- 6 Pages / 595.276 x 790.866 pts Page_size
- 15 Downloads / 143 Views
ORIGINAL PAPER
Improved Deep Trench Super-junction LDMOS Breakdown Voltage By Shielded Silicon-Insulator-Silicon Capacitor Lijuan Wu 1 & Qilin Ding 1 & Jiaqi Chen 1 Received: 12 August 2020 / Accepted: 7 October 2020 # Springer Nature B.V. 2020
Abstract Deep trench LDMOS is widely used in high-voltage level power devices. This paper proposes and optimizes a deep trench super-junction LDMOS with triangular charge compensation layer (TCCL DT SJ LDMOS), which solves the problem of charge imbalance in the super-junction region due to the Silicon-Insulator-Silicon (SIS) capacitance at both ends of the trench and improves the Breakdown Voltage (BV) of the device. This structure also helps to deplete the drift region at the bottom of the deep trench by adding P-buffer under the N-Pillars, which improves the doping concentration and reduces the specific on-resistance of the device. The simulation results show that compared with the Con. DT SJ LDMOS, the BV of the TCCL DT SJ LDMOS has been increased from 498V to 730V, and the power figure of merit (FOM) has increased by 12.8 MW / cm2(FOM = BV2 / Ron, sp). Keywords Triangular charge compensation layer . Super-junction . Deep trench . Breakdown voltage . Silicon-Insulator-Silicon (SIS)
1 Introduction Super-junction technology is become a major technological breakthrough in the history of power devices because it has achieved a compromise between BV and specific onresistance [1–3]. The development of integrated circuits is moving toward smaller sizes, however, SJ LDMOS is limited by the length of the drift region, so that it cannot achieve the high of breakdown voltage in smaller sizes [4]. Deep trench devices can fold the drift region under the same cell size [5, 6]. Introducing the super-junction technology into the deep trench device can solve the problem that SJ LDMOS is limited by the length of the drift region. In the conventional DT SJ LDMOS, due to the DT SIS capacitance effect, a large amount of charge is accumulated in the super-junction regions on the left and right sides of the trench, the charge in the super-junction
* Lijuan Wu [email protected] 1
Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering, School of Physics & Electronic Science, Changsha University of Science & Technology, Changsha 410114, China
region is unbalanced, and the breakdown voltage of the device is reduced [7]. In this paper, a triangular charge compensation layer (TCCL) is added to the super-junction region on both sides of the trench, it compensates the charge accumulated due to the SIS capacitance effect, so that the super-junction region reaches an ideal charge balance state, which optimizes the device’s electric field and improves the device’s breakdown voltage. Adding a P-buffer under the drift region at the bottom of the deep trench increases its optimal doping concentration and further reduces the specific on-resistance. The device is optimized by TCAD software and a feasible process flow is designed.
2 Device Structure and Mechanism TCCL DT SJ LD
Data Loading...