Improved Drive Capability of Silicon Nano Tube Tunnel FET Using Halo Implantation
- PDF / 2,129,952 Bytes
- 7 Pages / 595.224 x 790.955 pts Page_size
- 50 Downloads / 160 Views
ORIGINAL PAPER
Improved Drive Capability of Silicon Nano Tube Tunnel FET Using Halo Implantation Avtar Singh1 · Saurabh Chaudhary2 · Savitesh Madhulika Sharma3
· C. K. Sarkar4
Received: 24 July 2019 / Accepted: 4 December 2019 © Springer Nature B.V. 2020
Abstract In this paper, we focus on the improvement of comprehensive device performance of Silicon Nanotube Tunnel Field Effect Transistor (NT TFET) for ultra low power applications. In the design we have implanted 2nm Halo region at the source side of Si NT TFET for improving the subthreshold swing and short channel effects (SCEs). To prove the concept, the performance of Silicon Nanowire tunnel FET (NW TFET), Silicon Nanotube TFET without Halo (NT TFET) and Silicon Nanotube TFET with halo (NT FET HALO) implant are compared. The impact of halo doping profile on the Subthreshold swing, ON and OFF current are investigated. Further, the degradation of OFF state current due to Halo doping is controlled by lightly doped drain. Keywords TFET · Nanowire · Nanotube · Tunnel FET · Halo doping · Source pocket · Nanodevices
1 Introduction Nowadays, Tunnel FETs have attracted big attention due to their number of advantages over conventional MOSFET. The name Tunnel FET derives from the tunneling mechanism of charge carriers due to which the switching characteristics are excellent. The major advantage of the tunnel FET is its steep subthreshold swing generally, which is less than 60 mV/decade, low source drain resistance, Savitesh Madhulika Sharma
[email protected] Avtar Singh [email protected] Saurabh Chaudhary [email protected] C. K. Sarkar [email protected] 1
Department of Electronics and Comm. Engg., C.V. Raman College of Engineering, Bhubneshwar, India
2
Department of Electrical Engg., National Institute of Technology, Silchar, India
3
Department of Electronics and Comm. Engg., DVR & Dr. HS MIC College of Technology, Andhra Pradesh, India
4
Electronics and Telecommunication Engg. Dept., Jadavpur University, Kolkata, India
increased immunity with respect to process variation and low thermal budget [1–11]. Due to the rapid development in the fabrication technologies, it is conveniently possible to make the heterojunctions and tailored bandgaps for the better results at reduced supply voltage [12]. The possibility of synthesis of Si-nanotube FET are reported in [13]. So, tunnel FET can be used as a potential candidate for the future low power applications and nanodevices. The major drawback in Tunnel FET based devices is lower ON-State current, which is due to the larger tunneling resistance [14]. To improve the comprehensive device performance including the drive current capability, pocket implants have been employed at the source end, drain end and both ends [15]. However, the pocket implants helps in making the device immune to the short channel effects. Already designs like horizontal positioned source pockets [8] [16], pockets planted at vertical channel positions [17] and the underlap pockets are helpful in the improvement of narrow subthreshol
Data Loading...
