Improved Performance and Reliability in Aggressively-Scaled Nmos and Pmos Fets: I) Monolayer Interface Nitridation and I
- PDF / 2,950,663 Bytes
- 6 Pages / 414 x 635.4 pts Page_size
- 20 Downloads / 184 Views
Mat. Res. Soc. Symp. Proc. Vol. 592 ©2000 Materials Research Society
E 10
.
2.05 nm (SO 2)u(Sl 3N4)
10 10"
10
10
'10
.4
0
10 "
0m10
10
NMOSFET
10 10.1
S100
0.
10"4 -3
-2
-1
0
2
1
3
Applied Voltage Av) Fig. 1. Jg versus Vg for NMOS FETs with plasma-grown non-nitrided Si-SiO 2 interfaces and RPECVD oxide, nitride and oxyntirde gate dielectric layers. stacked gate dielectrics: i) an -2 nm plasma-processed oxide with - 0.6 nm formed by remote plasma-assisted oxidation (RPAO), and 1.4 nm by remote plasma-enhanced chemical vapor deposition (RPECVD), ii) an oxide/nitride stack, with -0.6 nm of oxide prepared by RPAO, and the nitride layer deposited by RPECVD [14], and iii) an oxide/oxynitride stack with -0.6 nm of oxide prepared by RPAO, and the oxynitride layer also deposited by RPECVD [14]. The oxynitride alloy has an approximate composition of (Si0 2 )0.5(Si 3N4 )0.5 or equivalently an N:O ratio of about 2:1. Studies of alloys with SiO2 fractions ranging from 0.3 to 0.7 have demonstrated that the maximum direct tunneling current reductions relative to devices with oxides were obtained for nearly equal SiO 2 and Si 3N 4 alloy fractions, i.e., (SiO 2)0.5(Si 3N 4)0.5.
Step: -0.5 V 1-- V- V. - -0.5---2.5V A
a6
- 20 pro/0.6 pm '
2_0 .20.~jS I0NJ, -- 2.00 (510,)sII,L.,
-5 :3.0
--
2.02 nm SiN, 2.03nm•1.0, -------.
-2.5
-2.0 -1.5 -1.0 -0.5 Drain Voltage (V)
2.06 (SO)jSiNj) .......... 2.03 nw SN 4 2.02 nm SIO, W&. 20 po/ 0A pm slop:0.5 V V -V -0.5- 2AV
10.0
-2
--------
-
12.5
-1
-3
-6
0.5
90 ) 70
".?t60 E
so
S20
10 0
(a)
2.05 nm. These devices NMOSFET
300 250.
A
E 200II
* 100
I
10 -
PMOSFrT lO x 100 Jm
0.3
7.5
100Amx 1001 Lm
-
350
-S40-
S30
-
400 -
A 2-02mnSN,
80
0.9 0.6 Ej jMV/cm)
.--.-.-.
1.0 1.5 2.0 25 Drain Voltage (V)
450 .
sIo, -0- Z03m 2.02 mn SIN,
.
a
0.07
110 •
10.0
5.0
-4
Fig. 2. Current drive form (a) PMOS and (b) NMOS FETs with EOT have - 0.6 nm SiO 2 interface layers, but no interface nitridation. 100'. 90I
12.5
50
0
1.2
I
@--2.03 nun SIO
-13 205nm (Si0,i.~(SI,Nd
A
2.02nmSkN.
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4
E., (W•lrn)
Fig. 3. Extracted mobility data from the current drive of Fig. 2 for PMOS and NMOS FETs.
178
10 .2 _10,
e PSFET 20pmlOAz lor S......W&.' 2030nm Si0,
10'
. .
U 10"
nm (S1O0),,(Si,Nj,,
C
SS.S 77.5mVcfor 810, SS. : 74A mV/dec for SI.N. 10" r .73! mve for (S1,I,(SiNj, -0.5 -1.0 -1.5 -2.0 -2.5 0.0
-
10 0
qn .
.311)
,v00
2.06 nm (Slo,)U(SINju
.
.
.
.
10
1.5
2.0
2.5
.
.
0.5
./......2.02
.
10'
S.S. - 74.9 mVIdec for SK), . 78.5 mV7dec for SikN4 S.S. - 74.5 mVldsc for (Sl0,),,(SIN,)
_0-"
Applied Gate Voltage (V)
10" 10"
Sn80O
2.03
10- 10, , 10"6
10' 10"
NMOSFET WIL - 20pmI0.6 pim nTIIn SlN4
110'
2.02 nm SiV -----..
-2.05
10-
10, *10,
104 10'
10' 10", |j0"1
3
Applied Gate Voltage (V)
Fig. 4. Sub-threshold behavior for the PMOS and NMOS FETs of Figs. 2 and 3. Figures 2(a) and (b) give current drive for PMOS and NMOS FETs, respectively for devices without interface nitrid
Data Loading...
