Uniformity of Gate Dielectric for I/O and Core HK/MG p MOSFETs with Nitridation Treatments
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https://doi.org/10.1007/s11664-020-08182-y 2020 The Minerals, Metals & Materials Society
INTERNATIONAL ELECTRON DEVICES AND MATERIALS SYMPOSIUM 2019
Uniformity of Gate Dielectric for I/O and Core HK/MG pMOSFETs with Nitridation Treatments CHING-CHUAN CHOU,1 TIEN-SZU SHEN,1 JIAN-MING CHEN,1 CHENGHSUN-TONY CHANG,1 SHEA-JUE WANG,2 WEN-HOW LAN,3,4 and MUCHUN WANG 1,5 1.—Department of Electronic Engineering, Minghsin University of Science and Technology, No. 1, Xinxing Rd., Xinfeng, Hsinchu 30401, Taiwan. 2.—Department of Materials and Resources Engineering, National Taipei University of Technology, Taipei 10608, Taiwan. 3.—Department of Electrical Engineering, National University of Kaohsiung, 700, Kaohsiung University Rd., Nanzih District, Kaohsiung 81148, Taiwan. 4.—e-mail: [email protected]. 5.—e-mail: [email protected]
Uniformity consideration in integrated-circuit manufacturing is an impressive task, especially in the field of nano-node semiconductors. The use of highdielectric-constant (high-K) materials to promote drive current in deep nanonode devices is also increasing. One solution involves enhancing the quality of the high-K dielectric layer as a gate dielectric with nitridation treatment. This study combines the aforementioned concerns in deep nano-node manufacturing and demonstrates their relationship. Given the electrical measurement of the wafers treated with decoupled plasma nitridation (DPN), a few desired key parameters, including drive current (IDS), threshold voltage (Vth), gate oxide capacitance per area (Cox), subthreshold swing (SS), and interface state density, in the design of p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) are observed. A uniformity comparison with different DPN processes is also performed, and the uniformity of the gate dielectric in input/output and core zones is discussed. Based on the uniformity distribution, lower SS values are obtained by adopting the low-temperature nitridation treatment after high-K dielectric deposition. The increased nitrogen concentration decreases the deviation, thereby indicating improved uniformity of SS values. Key words: Drive current, high-K, uniformity, interface state, nitridation, integrity
INTRODUCTION Although the design of integrated-circuit devices with deep-nano node processes is increasingly aimed towards a fin field-effect transistor (FinFET) structure,1–3 the planar structure of metal–oxide– semiconductor field-effect transistors (MOSFETs)4–6 still exhibits competitive benefits in terms of cost, uniformity,7 reliability,8–10 and yield. Efforts
(Received December 5, 2019; accepted April 29, 2020)
focus on continuously improving the drive current in high-performance computing structures11,12 including fin shape, photolithography,13,14 silicon– germanium channel,15 high-K (HK) gate dielectric,16–18 channel doping, source/drain strain,19 and barrier metal to adjust the work function.20,21 This approach does not change even when entering the sub-10 nano node. However, manufacturing cost22,23 and reliabili
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