Interaction Between Low Temperatures Spacers and Source Drain Extensions and Pockets for Both NMOS and PMOS of the 65 nm
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0912-C02-06
Interaction Between Low Temperatures Spacers and Source Drain Extensions and Pockets for Both NMOS and PMOS of the 65 nm Node Technology Nathalie Cagnat1, Cyrille Laviron2, Daniel Mathiot3, Pierre Morin4, Frédéric Salvetti5, Davy Villanueva5, Marc Juhel4, Marco Hopstaken5, and François Wacquant4 1 Ion Implantation R&D, STMicroelectronics, 850, rue Jean Monnet, Crolles, France, 38926, France, Metropolitan 2 LETI, CEA-Grenoble, Grenoble, France, 38054, France, Metropolitan 3 InESS, Strasbourg, France, 67037, France, Metropolitan 4 STMicroelectronics, Crolles, France, 38926, France, Metropolitan 5 Philips, Crolles, France, 38926, France, Metropolitan
ABSTRACT During the MOS transistors fabrication process, the Lightly Doped Drain areas (LDD, also called source-drain extension) are directly in contact with the oxide liner of the spacers stack. Previous works have established that Boron can diffuse from the LDD into the spacer oxide liner during the subsequent annealing steps, and that the amount of Boron loss depends on the Hydrogen content in the oxide, because it enhances Boron diffusivity in SiO2 [1, 2, 3]. In order to characterize and quantify the above phenomena, we performed test experiments on full sheet samples, which mimic either BF2 LDD over Arsenic pockets implants, or BF2 pockets under Arsenic or Phosphorus LDD implants. Following the corresponding implants, the wafers were covered with different spacer stacks (oxide + nitride) deposited either by Low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD). After appropriate activation annealing steps, Secondary Ion Mass Spectroscopy (SIMS) measurements were used to characterize the profiles of the various dopants, and the corresponding dose loss was evaluated for each species. Our experimental results clearly evidence that LPCVD or PECVD spacer stacks have no influence on the Arsenic profiles. On the other hand, Phosphorus and Boron profiles are affected. For Boron profiles, each spacer type has a different influence. It is also shown that Boron outdiffuses not only from the Boron doped LDD in direct contact with the oxide layer, but also from the "buried" Boron pockets lying under n-doped LDD areas. All these results are discussed in term of the possible relevant mechanism. INTRODUCTION The aggressive scale down of transistor length, required to improve further the density integration and device performance, requires to reduce strongly the junction depth of the source and drain areas, while maintaining acceptable sheet resistances. Thus the various steps affecting the final dopant profiles must be carefully controlled, especially the implantation steps (high doses, low energy, high current density) and the various anneals (deposition or activation steps) to minimize dopant diffusion.
However, the introduction of low thermal budget processes generates or enhances many specific physical phenomena that may change the integration and the behavior of the transistors. Among them, the interaction between Li
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