Integration of a Polymer Etch Stop Layer in a Porous Low K MLM Structure
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B2.11.1
Integration of a Polymer Etch Stop Layer in a Porous Low K MLM Structure Gregory C. Smith1, Neil Henis1,*, Richard McGowan1, Brian White2, Matthias Kraatz 1,3, Sri Satyanarayana1, Sharath Hosali1, Youfan Liu4, and Klaus Pfeifer1 1 SEMATECH, Austin Texas 2 Advanced Micro Devices Assignee at SEMATECH, Austin Texas 3 University of Texas, Austin, Texas 4 Intel Assignee at SEMATECH, Austin, Texas * currently at Bose, Incorporated ABSTRACT Two level metal structures were fabricated to test the efficacy of using an organic low K etch stop layer (OESL) in order to lower the effective dielectric constant for intralayer capacitance. The organic etch stop layer’s intrinsic capacitance of 3.3 compares with that of silicon carbide (~ 5) which constitutes the control of the experiment. This reduction represents a reduction of effective dielectric constant for the stack of about 10% to about 3.0. The process was optimized so as to achieve yield of via chains of a million 130 nm diameter vias, and effective K was measured. The target of 3.0 was achieved using this process. Interpenetration of the organic etch stop with the MSQ porous low K material was observed. INTRODUCTION Integrating high porosity dielectric layers between metal lines using a dual Damascene method requires protecting the sensitive layers from damage during the etch and ash processes. The shape of the bottom of the etch front in a porous low K material is difficult to control without sacrificing the anisotropy of the etch process, since the ion bombardment used to limit undercut of the mask also produces such artifacts as “trenching” along the edge of open features. Damage to the bottom of the trench can be significant, resulting in interlevel, and even intralevel leakage and very high effective dielectric constant, due to siloxane formation where methyl groups have been removed from the porous low K material by the etch chemistry. Two approaches to avoid or fix this problem involve the use of an etch stop layer (ESL) or development of damage free etching and ashing processes, or both. A diagram of a typical integration (one which we studied) is given in Figure 1. This structure is formed by first building metal 1, then the dielectric stack for the via and metal 2 levels, involving the dielectric barrier SiCN, which directly seals metal 1, then the dielectric stack for the via and metal 2 levels, and a thin SiO2 and SiC dual hard mask layer. An example of a moderate K structure with a silicon carbide etch stop layer is given in [3]. The top hard mask is then patterned, etching the SiC and stopping on the SiO2 . The via is then patterned and etched through the SiO2 layer, the M2 low K layer, and the etch stop layer. Then the via resist is stripped, and the M2 trench is etched through the SiO2 and the M2 low K dielectric, stopping on the etch stop layer using the patterned SiC hard mask to determine the M2 pattern. During the M2 etch, the via lands on the barrier, and goes through it, assuring that M1 is exposed only to
B2.11.2
Metal 2 (Cu)
CMP stop la
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