Integration of a silicon nanowire array into a photovoltaic device
- PDF / 292,309 Bytes
- 5 Pages / 595 x 842 pts (A4) Page_size
- 19 Downloads / 244 Views
1178-AA10-02
Integration of a silicon nanowire array into a photovoltaic device Simon Perraud1,*, Séverine Poncet1, Sébastien Noël1, Hakim Marko1,2, Emmanuelle Rouvière1, Philippe Thony3, and Régis Delsol3 1
CEA, LITEN, Laboratoire des Composants pour la Récupération d’Energie, 17 rue des Martyrs, F-38054 Grenoble Cedex 9, France. 2 Institut des Matériaux Jean Rouxel, Université de Nantes, CNRS, 2 rue de la Houssinière, BP 32229, F-44322 Nantes Cedex 3, France. 3 CEA, LITEN, Laboratoire des Composants Solaires, INES-RDI, Savoie Technolac, 50 avenue du Lac Léman, F-73377 Le-Bourget-Du-Lac, France. *Corresponding author. E-mail: [email protected] ABSTRACT Silicon nanowire arrays grown by chemical vapour deposition were successfully integrated into functional photovoltaic devices. A crucial planarization step, achieved by embedding the nanowires in a spin-on glass matrix and subsequent polishing of the front surface, allowed to deposit a continuous and uniform conductive film on top of the nanowire array, and thus to form a high-quality front electrical contact. The silicon nanowire array solar cells fabricated using this process exhibited a parasitic series resistance as low as 5 Ω.cm², which is a clear improvement compared to the recent literature. INTRODUCTION Using nanostructures is a promising route for third-generation photovoltaics [1]. In particular, silicon nanowires (SiNWs) grown by chemical vapour deposition (CVD) have been considered as building blocks for radial junction solar cells [2], which could enable energy conversion efficiencies comparable with conventional wafer-based solar cells, while reducing processing costs. Furthermore, quantum confinement effects in SiNWs could be employed for fabricating all-silicon multi-junction solar cells, with efficiencies exceeding the ShockleyQueisser limit for single-junction cells [3]. Promising results have been reported for SiNW array solar cells by Tsakalakos et al. [4,5] and Stelzner et al. [6]. However, the energy conversion efficiency obtained so far is about 0.1% [4-6], which is low compared to the typical performances of conventional wafer-based devices. One of the possible causes for such modest performances is the presence of a very high parasitic series resistance. Here, we propose an approach for integrating CVD-grown SiNW arrays into solar cells with low parasitic series resistance. EXPERIMENT The process used in this work for integrating SiNW arrays into solar cells is presented in figures 1 and 2. We focus on a simple device structure, consisting of n-type SiNWs grown on a p-type silicon substrate. The n-type SiNWs were prepared by CVD via the gold-catalysed
vapour-liquid-solid method [7, 8], on (100)-oriented silicon substrates of p-type conductivity (14-22 Ω.cm). Silane (SiH4) and phosphine (PH3) were used as the silicon precursor and the phosphorous n-type dopant precursor, respectively. The PH3/ SiH4 ratio was 2×10-3, corresponding to a nominal phosphorous concentration of 1×1020 cm-3. Electrical resistance measurements of individual SiNW
Data Loading...
