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U9.6.1/T4.6.1

Integration Processes and Properties of One Transistor Memory Devices Tingkai Li, Sheng Teng Hsu, Bruce Ulrich, Fengyan Zhang, Dave Evans Sharp Laboratory of America, Inc. 5700 NW Pacific Rim Blvd. Camas, WA 98607 [email protected] ABSTRACT MFMPOS (Metal, Ferroelectrics, Metal, Polysilicon, Oxide, and Silicon) one-transistor (1T) ferroelectric memory devices have been fabricated. However, the yield of 1T-memory devices is lower. We find that the main problems of 1T MFMPOS memory devices are shorts, opens, no memory window, smaller memory windows and blank. In order to solve these problems, we studied the reasons resulted in the problems. Then, the integration processes for one transistor memory device were optimized. Fabrication of nMOSFET 1T memory devices starts with shallow trench isolation (STI) on p-type Si. A gate oxide is thermally grown after p-well implantation. Phosphorus ions were implanted after polysilicon gate definition for the formation of self-aligned source, drain, and n-type floating gate. A damascene process using MOCVD PGO deposition and chemical mechanical polishing (CMP) were used to avoid etching damage. Electrodes for the ferroelectric capacitor, i.e., the floating Ir bottom electrode and Pt top electrode, are deposited by E-Beam evaporation. The area ratio of the top and floating gate electrodes is 1:1. After inter-level dielectric (ILD) deposition, contact etching stops on Pt at gate and on Si at source/drain (S/D) without difficulty because of high etch rate selectively to the Pt. Finally, the high quality 1T memory devices have been made. The one-transistor memory devices showed memory windows around 2 - 3V. The memory windows are almost saturated from operation voltage of 3V. The ratios of “on” state current to the “off” state current are closed to 8 - 9 orders. The one-transistor memory devices also show a very good memory characteristics and retention properties. INTRODUCTION One-transistor (1T) memory devices with MFMPOS and MFOS structures have been successfully fabricated recently [1-4]. MFMPOS one transistor memory devices show very good properties [3]. For the 1T-memory devices, memory window and retention properties are critical issues [3, 5-7]. The memory window of one transistor device is equal to the difference of the threshold voltage of the device when the ferroelectric material is poled toward the gate electrode and toward the gate insulator, respectively. The memory window of the device is equal to 2Pr/CFE (or 2Vc, the coercive voltage), where, Pr and CFE are the remanent polarization and capacitance of ferroelectric thin film, respectively. The remanent polarization value larger than 0.2 µC/cm2 is sufficient for low voltage, low power applications. It is not possible to maintain positive threshold voltage at “1” state if the Pr is too high. Therefore, an appropriate Pr and lower dielectric constant ferroelectric material is important for 1T memory transistor application. The retention problem for 1T-memory devices is the loss of memory windows as a functio