Interconnects and Contacts for VLSI Applications
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INTRODUCTION
The power of VLSI/ULSI (Very Large Scale Integration/Ultra Large Scale Integration) circuits is being increasingly realized through an ability to interconnect large numbers of components on a chip. In the foreseeable future, the intra-chip interconnects are expected to continue to dominate the physical area of VLSI/ULSI circuits. In order for these circuits to be commercially effective, the metalization technology (and indeed, the entire device processing technology) must respond to two industry-wide trends shown in Fig. I for DRAM's (dynamic random access memories), the traditional vehicle of choice for leading edge technology development: a. Ever higher integration levels (LSI - VLSI - ULSI), i.e. larger chip dimensions, longer and more numerous interconnections for exponentially increasing transistor counts that provide more functions per chips and hence lower system costs. b. Ever finer scaling of feature sizes (5p + 3p + 1,) and other consequences of scaling, e.g. shallower junction depths, thinner oxides, and shorter channel lengths to enable superior device performance. The IMb DRAM chip,' shown in Figure 2, fits nicely with the above trend plots. This circuit utilizes three levels of conductors to interconnect over one million each of the transistors and capacitors on a chip. The first conductor level consists of doped poly-Si capacitor field plates, the second level utilizes TASi 2/n+ poly-Si for gates and word lines, whereas the third level is made up of Si-doped Al bit lines (Figure 3).
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Figure I
Decrease in the critical feature size and increase in the longer chip dimension, with time, of DRAM chips.
BPSG INTERLEVEL INSULATOR
Figure 2
Micrograph of a IMb DRAM.
Figure 3
Schematic cross-section through a memory cell.
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The combination of larger chip dimensions and finer scaling generates several technology concerns relating to parasitics, defect density and generic reliability. Control of these three factors has turned out to be the main driving force for many technological improvements in VLSI circuits. II.
PARASITICS
In practice, all VLSI circuits are associated with parasitic resistance and capacitances that tend to offset the performance advantages of small geometry transistors. Performance degradation due to parasitics is now believed to be the factor most likely to limit continued progress towards fine-line VLSI. Two important examples of parasitics that can be controlled through choice of metalization are the RC time constant and the source/drain series resistance. The RC time constant or rise time for a distributed transmission line increases as the square of the length of the interconnect. At near micron and submicron design rules, the capacitive coupling between adjacent lines and fringing capacitance to the substrate become dominant components of the total capacitance C. Figure 4 shows that the rise time of even high
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