Mixed CNT bundles as VLSI interconnects for nanoscale technology nodes
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Mixed CNT bundles as VLSI interconnects for nanoscale technology nodes Gurleen Dhillon1 · Karmjit Singh Sandha1 Received: 30 May 2020 / Accepted: 3 September 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract The continuous miniaturization of very large-scale integration devices impacts the performance of integrated circuits. The performance of existing interconnect materials such as copper has become saturated beyond the deep-submicron technology node, motivating the search for new interconnect materials that could be efficiently employed in such circuits. In this study, a temperature-dependent analysis is performed to determine the propagation delay, power dissipation, and power–delay product of copper, single-walled carbon nanotubes (SWCNTs), multiwalled carbon nanotubes (MWCNTs), double-walled carbon nanotubes (DWCNTs), and mixed (multi- and double-wall) carbon nanotube bundle (MDCB) structures. The performance of these bundled structures is examined with the help of a complementary metal–oxide–semiconductor driver interconnect load system at various temperatures (200–500 K) and technology nodes (22 and 16 nm). The proposed novel mixed structure with MWCNTs at the periphery and DWCNTs in the center is interesting due to the combination of the excellent conducting properties of DWCNTs and the reduction of the net capacitive coupling due to the MWCNTs. Indeed, it is observed that this MDCB interconnect structure can outperform not only copper interconnects but also the SWCNT, MWCNT, and DWCNT structures. Such mixed structures could be used as interconnect materials in high-speed integrated circuits at future nanotechnology nodes. Keywords Carbon nanotubes (CNTs) · Multiple single conductor (MSC) · Multi-wall and double-wall carbon nanotube bundle (MDCB) · Power–delay product (PDP) · Equivalent single conductor (ESC)
1 Introduction Over recent years, CNTs have been successfully used as a very large-scale integration (VLSI) interconnect material at nodes in the nanometer regime as an alternative to copper, because the resistance of copper exhibits unwanted rises due to adverse effects such as electromigration, surface roughness, and grain-boundary scattering [1–4]. These unwanted resistance increases result in an increased propagation delay and power dissipation in integrated circuits [1, 4–8]. A single graphene sheet in the shape of a hollow cylinder forms a single-walled CNT, while when multiple hollow nanotubes are placed concentrically, they form a multiwalled * Karmjit Singh Sandha [email protected] Gurleen Dhillon [email protected] 1
Thapar Institute of Engineering and Technology, Patiala, India
CNT structure [3, 6]. The DWCNT structure consists of two concentric graphene sheets. Furthermore, the metallic or semiconducting nature of a nanotube is determined by the direction in which the graphene sheet is rolled. Metallic nanotubes are useful for interconnect applications [9–13]. These nanotubes are placed in parallel to form a bundle, which helps to decre
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