Interface Engineering During Epitaxial Growth of High-K Lanthanide Oxides on Silicon
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0917-E10-04
Interface Engineering During Epitaxial Growth of High-K Lanthanide Oxides on Silicon H. Joerg Osten1,2, Malte Czernohorsky1, Eberhard Bugiel1, Dirk Kuehne2, and Andreas Fissel2 1 Institute of Electronic Materials and Devices, University of Hannover, Appelstr. 11A, Hannover, D-30167, Germany 2 Information Technology Laboratory, University of Hannover, Schneiderberg 32, Hannover, D30167, Germany
ABSTRACT We investigated the influence of additional oxygen supply and temperature during the growth of thin Gd2O3 layers on Si(001) with molecular beam epitaxy. Additional oxygen supply during growth improves the dielectric properties significantly; however too high oxygen partial pressures lead to an increase in the lower permittivity interfacial layer thickness. The growth temperature mainly influences the dielectric gate stack properties due to changes of the Gd2O3/Si interface structure. Optimized conditions (600 °C, pO2 = 5·10-7 mbar) were found to achieve equivalent oxide thickness values below 1 nm accompanied by leakage current densities below 1 mA/cm² at 1 V.
INTRODUCTION Scaling of semiconductor devices has reduced the thickness of the gate dielectric. The exponential increase of gate leakage and a reduced reliability necessitate a replacement of traditional SiO2 [1]. Alternative material systems with higher dielectric constant (high-K dielectrics) enable an increase of physical thickness while maintaining the gate capacitance. Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 µm CMOS technology. The most promising candidates are metal oxides [2]. Unfortunately, a number of these materials are not thermally stable on silicon [3]. The Si/dielectric interface properties influence the device performance significantly. Often the interface changes during and after the growth. The formation of SiO2 and/or metal silicate interfacial layers can occur when these materials are deposited upon silicon or during subsequent annealing processes. The occurrence of an interfacial layer of SiO2 or another low permittivity material will limit the highest possible gate stack capacitance, or equivalently, the lowest achievable equivalent oxide thickness (EOT) value. A good interface requires either that the oxide is amorphous, or that it is epitaxial and lattice-matched to the underlying silicon. Amorphous dielectrics are expected to be able to adjust the local bonding to minimize the number of Si dangling bonds at the interface. The alternative is to use an epitaxial oxide. This involves more effort, but it has the advantage of enabling defined interfaces engineering. Molecular beam epitaxy (MBE), known for its superior capability in atomic level engineering and interface control, has been used in the epitaxial growth of various high-K materials [4-6]. Here, we will present results for crystalline lanthanide oxides on silicon with the Ln2O3 composition (Ln = Pr, Nd and Gd) in the cubic bixbyite structure grown by solid state MBE.
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