Investigation of N+ pocket-doped junctionless vertical TFET and its digital inverter application in the presence of true
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Investigation of N+ pocket‑doped junctionless vertical TFET and its digital inverter application in the presence of true noises Vandana Devi Wangkheirakpam1 · Brinda Bhowmick1 · Puspa Devi Pukhrambam1 Received: 31 October 2019 / Accepted: 9 September 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract This paper reports the investigation of conventional junctionless tunnel FET (JL-TFET) and N+ pocket-doped junctionless vertical tunnel FET (JL-VTFET). The investigation is done by analyzing the effect on the ID–VGS characteristics (a) under a wide range of temperature and (b) in the presence of acceptor interface trap charges. This work also examines the performance of noise and its impact on the digital inverter. Comparison has been made on the TCAD simulated results of both the devices. It is observed that the degradation of drain current (ID) is less in JL-VTFET and also it has better noise performance than that of conventional JL-TFET. Its net drain current noise spectral density (Sid) reaches 10–15 A2/Hz till 1 MHz and decreases with further increase in frequency. The contributions of generation–recombination noise and flicker noise are found to be more in low and moderate frequency, whereas diffusion noise dominates at high frequency. Furthermore, the impact of interface traps is studied using complementary JL-VTFET digital inverter application and compared with the one without interface traps. The transient characteristics show an average delay of 15 ps and 27 ps in the absence and presence of interface traps, respectively. Keywords Junctionless tunnel field effect transistor (JL-TFET) · Junctionless vertical TFET (JL-VTFET) · Interface trap charges · Drain current noise spectral densities (Sid) · Gate voltage noise spectral densities (Svg)
1 Introduction The commercial requirements of the semiconductor industries to increase the device functionalities on chip leads to the shrinking of the device dimensions in MOSFETs [1, 2]. The benefits of scaling of conventional MOSFETs includes the device compactness, cost-effectiveness, enhanced current drivability and improved high-frequency performance. However, scaling can cause various short channel effects such as velocity saturation, hot carrier effect, and draininduced barrier lowering (DIBL) effect which deteriorates the low power performance of the device. MOSFETs also have subthreshold swing (SS) limit of 60 mV/dec due to their dependence on thermal voltage. Tunnel field effect transistor (TFET) is a promising emerging device, which can overcome the aforesaid issues of MOSFET [3, 4]. TFET * Vandana Devi Wangkheirakpam [email protected] 1
Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, Assam 788010, India
is gated p-i-n diode whose current conduction is due to the quantum tunneling of carriers from the valence band of the source to the conduction band of the channel [5, 6]. It has low leakage current and an SS lower than the thermal limit of MOSFET, making it an encouraging
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