Investigation of Short Channel Effects (SCEs) and Analog/RF Figure of Merits (FOMs) of Dual-Material Bottom-Spacer Groun
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ORIGINAL PAPER
Investigation of Short Channel Effects (SCEs) and Analog/RF Figure of Merits (FOMs) of Dual-Material Bottom-Spacer Ground-Plane (DMBSGP) FinFET Vadthiya Narendar 1 & Pallavi Narware 2 & V. Bheemudu 3 & Bhukya Sunitha 4 Received: 24 July 2019 / Accepted: 7 November 2019 # Springer Nature B.V. 2019
Abstract FinFETs are popular and forefront runner in integrated circuits (ICs) technology due to exceptional scalability and suppressed short channel effects (SCEs). The bottom spacer (BP) concept is adopted in FinFET to achieve ameliorated short-channel, reduced self heating issues and to solve width quantization effect. The dual-material-gate (DMG) concept provides novel features like threshold voltage roll-up, transconductance enhancement and suppression of SCEs by work function engineering. Further, the ground-plane (GP) concept is also introduced to minimize the interaction between source and drain region which results in suppressed drain induced barrier lowering (DIBL). This paper investigates the systematic analysis of novel DMBSGP FinFET. The electrical performance parameters are extracted for different bottom spacer height (BSH) and workfunction differences (ΔW). The analog/RF figure of merits (FOMs) such as transconductance (gm), output conductance (gd), transconductance generation factor (gm/ID), early voltage (VEA), intrinsic gain (AV), cut-off frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are examined for different BSH of DMBSGP FinFET using 3-D ATLAS device simulator. Keywords Bottom spacer (BS) . Dual-material gate (DMG) . FinFET . Ground-plane (GP) . Drain induced barrier lowering (DIBL)
1 Introduction The possibility of scaling metal-oxide-semiconductor (MOS) devices [1] and available scaling relationship to reduce the size of conventional MOSFET [2] have made the
* Vadthiya Narendar [email protected] 1
Department of Electronics & Communication Engineering, National Institute of Technology Warangal, Warangal, Telangana 506004, India
2
Department of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Allahabad, U.P. 211004, India
3
Department of Electronics & Communication Engineering, G. B. Pant Govt. Engineering College, Okhla Phase-III, New Delhi 110020, India
4
Department of Electronics & Communication Engineering, Kodada Institute of Technology & Science for Women, Kodada, Telangana 508206, India
complementary MOS (CMOS) technology commercially successful. The power dissipation becomes manifold as the CMOS devices are scaled into deep sub-micrometer regimes due to increase in leakage current (which occurs mainly because of threshold voltage reduction), drain-induced barrier lowering (DIBL), threshold voltage roll-off, temperature effect, narrow width effect, gate-induced drain leakage (GIDL), body effect and gate oxide tunnelling [3]. Also, the conventional MOSFETs have problem like high parasitic capacitance, latch-up and surface mobil
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