Embedding Two P + Pockets in the Buried Oxide of Nano Silicon on Insulator MOSFETs: Controlled Short Channel Effects and
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ORIGINAL PAPER
Embedding Two P+ Pockets in the Buried Oxide of Nano Silicon on Insulator MOSFETs: Controlled Short Channel Effects and Electric Field Zahra Aghaeipour 1 & Ali Naderi 1 Received: 13 October 2019 / Accepted: 12 December 2019 # Springer Nature B.V. 2019
Abstract This paper proposes an efficient structure for nanoscale silicon on insulator (SOI) MOSFETs. Two P+ pockets are considered in buried oxide, a pocket under source region and another under channel. Also an N type region with low doping density is considered inside the drain region. By applying the mentioned modifications in buried oxide, short channel effects such as DIBL and subthreshold swing are reduced. Lattice temperature is successfully managed and controlled. The leakage current, floating body effect, and gain voltage, have better values in comparison with conventional structure. Inserted low doping region lowers the maximum electric field at drain side and consequently lessens the breakdown probability. The proposed device with mentioned modifications is suitable to be used in high-temperature, and low dimensional applications. Keywords Nano MOSFET . Short channel effects . Electric field . Tunneling . Leakage current
1 Introduction In recent years the development in semiconductor technology results in smaller transistors. By reducing the size of transistors, the performance, switching speed and density of on chip devices have been improved [1–3]. The need to integrate circuits has greatly increased the importance of using nanoscale devices [4]. Among nanoscale devices, the metal-oxidesemiconductor field-effect transistors (MOSFETs) are one of major devices in research and industry [5]. When the transistor dimensions reach the nano level, the assumption of uniform carrier density distribution in the transistor channel is not correct anymore. The low control of gate on channel electrostatics causes changes in the transistor characteristics and creates unpredictable short channel transistor parameters such as drain induced barrier lowering (DIBL) and leakage current. Shortening the channel length increases the dependence of the device output parameters on variations in device physical parameters of the device such as channel length as well as reducing the gate controllability on the drain * Ali Naderi [email protected] 1
Electrical Engineering Department, Energy Faculty, Kermanshah University of Technology, Kermanshah, Iran
current [6]. As the channel length shrinks, there are disadvantages and problems, called short channel effects (SCE) [7–9]. It is important to reduce the negative effects of channel shortening on transistor performance to increase the device efficiency and reliability. Silicon-on-insulator (SOI) is an efficient technology which has been applied on MOSFETs. SOI technology enjoys the benefits of silicon dioxide (SiO2) layer which is under the channel region as buried oxide (BOX). The BOX can be developed by two conventional mechanisms including oxygen implantation or oxidation of silicon. This BOX enhances the transi
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