The Effects of the LDD process on Short-channel effects in Nanoscale Charge Trapping Devices
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0997-I03-13
The Effects of the LDD process on Short-channel effects in Nanoscale Charge Trapping Devices Moon Kyung Kim1, SooDoo Chae2, Chung Woo Kim2, Joo Yeon Kim3, Jo-won Lee4, and Sandip Tiwari1 1 Electrical and Computer Engineering, Cornell University, Ithaca, NY, 14850 2 Semiconductor Business, Samsung Electronics Co., Yongin-City, Kyunggi-Do, Korea, Republic of 3 School of Electricity & Electronics, Ulsan college, Ulsan, 682-715, Korea, Republic of 4 Tera-level Nano Devices, Seoul, Korea, Republic of ABSTRACT In the use of single/few electrons in distributed storage for non-volatile, low power and fast memories, providing statistical reproducibility at the nanoscale is a key challenge since relative variance has n dependence and we are working with limited number of storage sites. We have used defects at interfaces of dielectrics to evaluate this reproducibility and evaluate the performance of memories. These experiments show that nearly 100 electrons can be stored at 30 nm dimensions, sufficient for reproducibility, and that a minimum of tunneling oxide thickness is required to assure reliable retention characteristics. Different tunneling oxide thicknesses and the effect of LDD process is investigated to draw these conclusions.
INTRODUCTION Many electronic applications require non-volatile memories (NVM) to retain information even when power is turned off or program the source of operating code that needs to be downloaded for the necessary computation [1]. Implementing non-volatile, low power and fast memories at short dimensions is the main issue in flash memory devices. Among the approaches being adopted are use of storage of single or a few electrons such as in nanocrystal memories, and other modifications such as the use of SONOS, silicon-oxide-oxide-silicon or back-floating gates [2][3][4]. Silicon nitride and its interface with silicon dioxide provides an alternative for this charge storage where the highly localized storage of charge at increased number of sites may allow a further scaling of the insulator thickness and a trade-off in other attributes vis-‡-vis nanocrystal memories. The reduction of the gate stack thickness is preferable but there are limits to it arising from the energy scale, length scale, and time scale of the injection, storage and removal processes associated with the specific defects employed [5]. This work focuses, experimentally, on evaluating the thickness of tunneling oxide and retention attributes of highly localized defects. Additionally, this paper briefly compares the short-channel effects between the device with LDD implantation and the device without LDD process. Both devices show attractive endurance and programming properties.
EXPERIMENT
Nanoscale SONOS devices are fabricated on SOI substrates which is depicted in Figure 1. Mixed-mode lithography, combining optical and electron-beam, is employed to obtain narrow channel widths and short channel lengths on SOI wafers using deep-etched alignment marks. Following the active region definition on the thinned silicon
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