Large-Area, Device Quality GaN on Si Using a Novel Transition Layer Scheme
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Large-Area, Device Quality GaN on Si Using a Novel Transition Layer Scheme Pradeep Rajagopal, Thomas Gehrke, John C. Roberts, J. D. Brown, T. Warren Weeks, Edwin L. Piner, Kevin J. Linthicum Nitronex Corporation, 628 Hutton Street, Suite 106, Raleigh, NC 27606 ABSTRACT The emergence of III-nitride technology and fabrication of high quality GaN based devices is possible due to the advances in the heteroepitaxial growth of III-N thin-films on latticemismatched substrates. Typically, the substrate of choice is either SiC or sapphire. We have adopted 100mm Si as our substrate of choice; uniform substrates of high quality are inexpensive and plentiful due to decades of use in the microelectronics industry. Growth of device quality GaN on Si is challenged by the ~17% lattice mismatch and an additional thermal expansion coefficient (TEC) mismatch of ~56%. In order to accommodate this strain and TEC mismatch between Si and GaN, a novel transition layer was designed, grown and successfully optimized, obviating the need for either a PENDEO® based overgrowth process or a SiC interlayer-based process. This growth technique (SIGANTIC®) does not require any wafer conditioning prior to growth and thus reduces the process complexity and maintains the cost effectiveness of the GaN on Si strategy. We will report on this manufacturable 100mm MOCVD heteroepitaxial process that consistently produces device quality AlGaN/GaN heterostructures with two dimensional electron gas (2DEG) mobilities typically around 1400 cm2/Vs at room temperature. Structural and electrical properties as determined by optical reflectance, atomic force microscopy, capacitance-voltage and van der Pauw Hall measurements, which are measured across the 100mm wafer, will be presented. Device results will be mentioned to show continuous wave (CW) RF operation at 2 GHz with competitive power output, gain and power added efficiency (PAE). INTRODUCTION Growth of high quality GaN on Si (111) can be achieved only by addressing the significant levels of lattice misfit (~17%) and TEC (~ 56%) mismatch. A schematic of the lattice misfit is shown in Figure 1 (a). It is clear, that the lattice misfit effects will dominate the Si/III-N interface, where a high density of misfit dislocations are expected to form during growth. For example, the choice of using AlN as a nucleation layer on Si (111) results in the formation of an estimated maximum of ~3 x 1012 cm-2 misfit dislocations near the Si/AlN interface. It will be shown that despite the high density of defects that are expected to be present in the AlN layer, these do not appear to impact the 2DEG properties of subsequently deposited AlGaN/GaN device layers. The TEC mismatch between GaN and Si (αGaN║ = 5.59x10-6/K, for T >= 300K, αSi = 3.59 x 106 /K @ 300K1) poses a completely different challenge and is shown in figure 1 (b). The TEC mismatch results in stress (σ) within the film, which can be calculated from equation 1 as, σ = ∆α∆TEf
(1)
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Where ∆α is the TEC mismatch between GaN and Si, ∆T is the difference
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