Stress engineering using AlN/GaN superlattices for epitaxy of GaN on 200 mm Si wafers
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Stress engineering using AlN/GaN superlattices for epitaxy of GaN on 200 mm Si wafers
Jie Su, Eric A. Armour, Balakrishnan Krishnan, Soo Min Lee, and George D. Papasouliotis Veeco MOCVD Operations, 394 Elizabeth Avenue, Somerset, NJ 08873, USA
ABSTRACT Stress control using AlN/GaN superlattices (SLs) for epitaxy of GaN on 200 mm Si (111) substrates is reported. Crack-free 2 m GaN layers were grown over structures containing 50 to 100 pairs of 3-5 nm AlN/10-30 nm GaN SLs. Compressive and tensile stress can be precisely adjusted by changing the thickness of the AlN and GaN layers in the SLs. For a constant period thickness, the effects of growth conditions, such as growth rate of GaN, V/III ratio during AlN growth, and growth temperature, on wafer stress were investigated. INTRODUCTION AlGaN based high-electron-mobility-transistors (HEMTs) grown on silicon are the focus of considerable research efforts, due to the availability of low-cost, large-diameter substrates and the potential for integration with Si-based technologies[1-2]. However, epitaxy of GaN on Si (111) is challenging because of eutectic Ga-Si reactions, and the large mismatch in lattice constant and thermal expansion coefficient (CTE) between GaN and Si. The large lattice mismatch can result in a high density of misfit and threading dislocations in the epi-layers, along with significant intrinsic stress causing large wafer bow during growth, which, in turn, can lead to large gradients in growth temperature across the wafer, resulting in non-uniformity in epilayer thickness, alloy composition, and device performance [3-4]. Compressive intrinsic stress has to be intentionally built-in the GaN layer during epitaxy to compensate for the large tensile thermal stress that occurs during wafer cool-down. Intermediate layers such as graded or stepped AlxGa1-xN layers [5-6], and strained AlN/(Al)GaN superlattices (SLs) [7-9] have been proven effective in building compressive intrinsic stress and filter dislocations within the growth plane. In this article, we are reporting on stress control using AlN/GaN SLs for epitaxy of GaN on 200 mm Si substrates. Compressive and tensile stress can be precisely adjusted by changing the thickness of the AlN and GaN layers in the SLs. The effects of growth conditions, such as growth rates of GaN, V/III ratio during AlN growth, and process temperature, on wafer stress are examined for a SL structure of constant period thickness. EXPERIMENT DETAILS The epitaxy process experiments were carried out in a state-of-art Veeco PropelTM Power GaN MOCVD system, which encompasses a 200 mm single wafer MOCVD reactor. The system is equipped with a DRT-210 in-situ process monitor (integrated pyrometer-reflectometerdeflectometer unit) for wafer temperature, reflectance and wafer curvature measurements. The
evolution of growth stress can be monitored in real-time through the change of wafer curvature using the in-situ deflectometer [10-12]. The epitaxy of GaN with AlN/GaN SLs was performed on 200 mm Czochralski (CZ) on-axis Si (111) wafers
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