Location Control of Crystal Grains in Excimer Laser Crystallization of Silicon Thin Films for Single-Grain TFTs
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A4.2.1
Location Control of Crystal Grains in Excimer Laser Crystallization of Silicon Thin Films for Single-Grain TFTs Hideya Kumomi1, Hiroaki Wakiyama2, Gou Nakagawa2, Kenji Makihira2, and Tanemasa Asano2 Leading Edge Technology Development Headquaters, Canon Inc., 5-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243--193, Japan. email: [email protected] 2 Center for Microelectronic Systems, Kyushu Institute of Technology, Kawazu, Iizuka 820-8502, Fukuoka, Japan 1
ABSTRACT Location of crystal grains is controlled in excimer laser crystallization (ELC) of amorphous Si (a-Si) thin films, aiming at a high-performance single-grain thin film transistor (TFT) whose channel is inside a single crystal grain with no grain boundary in the channel. The location control is achieved by manipulating seed-crystal forming sites in the starting thin film. The sites are small portions of the a-Si thin film, typically 1 µm in diameter, only in which nanometer-sized crystallites are embedded in the amorphous matrix. During the ELC, at least one crystallite survives the melting duration and serves as a seed crystal for the resolidification of the surrounding molten silicon. As a result, large crystal grains are formed at the predetermined sites. The TFTs whose channels are fabricated at the location-controlled crystal grains exhibit higher performance than the random polycrystalline Si (poly-Si) TFTs. INTRODUCTION Rapid melting and resolidification (RMR) of a-Si thin films by laser annealing has been applied to the production of low-temperature poly-Si (LTPS) for the TFTs over glass substrates, which constitute not only the pixel switches but the peripheral driver circuits for active-matrix flat-panel displays. However, further system integration into the panel demands both the enhancement of the performance and the device-to-device uniformity. As always happens with poly-Si TFTs formed by other means, grain boundaries (GBs) included in the TFT channel are one of the primary factors that hinder the carrier transport and deteriorate the TFT performance. There is a general methodology for eliminating GBs from the channel region controlling the location of GBs by location control of the crystal grains [1]. It has been demonstrated that the single-grain TFTs fabricated by solid-phase crystallization (SPC) and the circuits using them exhibits higher performance than the random poly-Si TFTs [2]. There have been reported also in the RMR, various approaches to the one- or two-dimensional control of the GB location, which utilize either spatial temperature distribution or grain-filtering techniques [3]. Different from these previous approaches, we have proposed a new method using the starting thin films having multiple regions different in state for the two-dimensional control of the GB location in the RMR, relying neither on the temperature distribution nor the grain filtering [4]. This paper presents the enlargement of the location-controlled crystal grain which is large enough to include the TFT channel and the preliminary results of the
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