Low-energy error correction of NAND Flash memory through soft-decision decoding
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Low-energy error correction of NAND Flash memory through soft-decision decoding Jonghong Kim and Wonyong Sung*
Abstract The raw bit error rate of NAND Flash memory increases as the semiconductor geometry shrinks for high density, which makes it very necessary to employ a very strong error correction circuit. The soft-decision-based error correction algorithms, such as low-density parity-check (LDPC) codes, can enhance the error correction capability without increasing the number of parity bits. However, soft-decision error correction schemes need multiple precision data, which obviously increases the energy consumption in NAND Flash memory for more sensing operations as well as more data output. We examine the energy consumption of a NAND Flash memory system with an LDPC code-based soft-decision error correction algorithm. The energy consumed at multiple-precision NAND Flash memory as well as the LDPC decoder is considered. The output precision employed is 1.0, 1.4, 1.7, and 2.0 bits per data. In addition, we also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. The experiment was conducted with 32-nm 128-Gbit 2-bit multi-level cell NAND Flash memory and a 65-nm LDPC decoding VLSI. Keywords: NAND Flash memory, LDPC, Low-density parity-check codes, Multi-precision sensing operation, Soft-decision decoding, Low energy
Introduction NAND Flash memory is widely used for handheld devices and notebook PCs because of its high density and low power consumption. As the semiconductor geometry shrinks, the error performance of NAND Flash memory becomes worse, thus it is greatly needed to increase the reliability by using memory signal processing and forward-error correction (FEC) methods. Among various FEC codes, Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon (RS) codes have widely been used for NAND Flash error correction [1-3]. However, because of severe performance degradation of recent NAND Flash memory devices, more advanced FEC codes are needed. Low-density parity-check (LDPC) codes [4] show excellent error correcting performance close to the Shannonlimit when decoded with the belief-propagation (BP) algorithm [5] using soft-decision information. LDPC codes have successfully been applied to many communication systems such as DVB-S2 [6], IEEE 802.3an [7],
*Correspondence: [email protected] Department of Electrical Engineering and Computer Science, Seoul National University, Gwanak-gu, Seoul 151-744 Korea
and IEEE 802.16e [8]. However, despite of good characteristics of LDPC codes, their application to NAND Flash memory is not straightforward because multiple precision output data are needed for exploiting the advantages of LDPC algorithms that show high performance with softdecision decoding. Moreover, multiple sensing operations and delivering multiple precision data also increase the energy consumption of NAND Flash memory. In this article, we analyze the energy consumption of a NAND Flash memory error correction system that adopts LDPC soft-decis
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