Low temperature CVD growth of graphene nano-flakes directly on high K dielectrics
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Low temperature CVD growth of graphene nano-flakes directly on high K dielectrics Mark H. Rümmeli1,2, Alicja Bachmatiuk1, Arezoo Dianat2, Andrew Scott1, Felix Börrnert1, Imad Ibrahim1,2, Shasha Zhang1, Ewa Borowiak-Palen3, Gianaurelio Cuniberti2,4 and Bernd Büchner1 1 Leibniz-Institut für Festkörper- und Werkstoffforschung Dresden e. V., PF 27 01 16, 01171 Dresden,Germany 2 Technische Universität Dresden, 01062 Dresden, Germany 3 Zachodniopomorski Uniwersytet Technologiczny, Pulaskiego 10, 70322 Szczecin, Poland 4 Division of IT Convergence Engineering and National Center for Nanomaterials Technology,POSTECH, Pohang 790-784, Republic of Korea ABSTRACT The potential of MgO and ZrO2 as catalytically active substrates for graphene formation via thermal CVD is explored. Experimental observations show the growth of single and multilayer graphene nano-flakes over MgO and ZrO2 at low temperatures. The graphene nano-flakes are found to anchor at step sites. Ab initio calculations indicate step sites are crucial to adsorb and crack acetylene. INTRODUCTION Interest in graphene since its isolation in 2004 [1] has rapidly escalated and now with Geim and Novosalov being awarded the 2010 Nobel prize for physics, it looks set for even greater attention. It has been described as nature’s thinnest elastic material and its exceptional mechanical and electronic properties make it an extremely exciting material. Within the realm of electronics, it is its one atoms thickness, planar geometry, high current-carrying capacity and thermal conductivity and potential to open a gap when existing as a narrow ribbon that hold particular promise. These features make it ideally suited for further miniaturizing electronics to form ultra-small devices and components for future semiconductor technology. In order for graphene to realize its potential in electronics various obstacles need to be overcome. One of the more important aspects is its actual synthesis. Various routes exist to synthesize graphene however most are not best suited for integration in to current silicon technology. The primary routes are through graphite exfoliation, epitaxial graphene, graphene oxide and chemical vapour deposition. Most of these routes require the graphene be transferred onto a dielectric or, as in the case of SiC, require high temperatures. In order to use them in field-effect transistors at room temperature one needs to modify graphene’s semi-metallic nature so as to open a band gap. When existing as narrow strips (nanoribbons) quantum confinement effects lead to band gap formation [2]. Most band gap engineering routes use multiple lithographic steps to fabricate a graphene device. This leads contamination and disorder to the flake. Dry lithography-free techniques can help [3], but technical difficulties still remain. Another approach is chemical modification, for example, graphene oxide in which hydroxyl and other chemical groups attach to graphene. Although the technique is able to lift the degeneracy of the ʌ band at the Fermi level of graphene, it is diffic
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