Manufacturable 300mm Wafer Thinning for 3D Interconnect Applications
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1249-E01-02
Manufacturable 300mm Wafer Thinning for 3D Interconnect Applications Jamal Qureshi1, 2, Raymond Caramto1, 2, Stephen Olson1, 2, Jerry Mase1, 2, Toshihiro Ito3, and Eiichi Yamamoto3 1
3D Interconnect, SEMATECH, Albany, NY, USA. College of Nanoscale Science and Engineering, University at Albany-SUNY, Albany, NY, USA. 3 Process R and D, OKAMOTO Machine Tool Works, LTD., Annaka, Gunma, Japan. 2
ABSTRACT 3D interconnect wafer-to-wafer or die-to-wafer integration requires a wafer thinning operation to expose copper (Cu)-filled through-silicon vias (TSVs) from the backside of the wafer. The wafer thinning flow uses edge trim, backgrind, backpolish, and chemical mechanical polishing (CMP). This paper presents an overview of the wafer grinding process. We have demonstrated the capability to edge-trim and backgrind 300 mm TSV and non-TSV wafers down to 30 microns (μm) while bonded to a handle wafer. TSV wafers were further processed on a CMP tool to remove the last few microns of Si, exposing the Cu-filled TSVs. Metrology techniques were used to inspect and measure the wafer edge trim and final thinned wafer thickness. The quality of the thinned wafer was characterized by atomic force microscopy (AFM) to observe surface roughness and by transmission electron microscopy (TEM) to quantify crystalline damage below the surface of the thinned wafer. Further characterization included measuring wafer thickness, total thickness variation (TTV), bow, and warp. Exposed TSVs were characterized by laser microscope to measure the height of Cu protrusions. These critical elements of a manufacturing-worthy 300 mm wafer thinning process for 3D are discussed. INTRODUCTION – BACKGRIND PROCESS FLOW The overall thickness of stacked chips must be thinned so that they can be assembled into a smaller package. Currently, IC chips are stacked by grinding the backside of each chip and connecting the chips by wire bonding. Through-silicon vias (TSVs) are being pursued because they have the potential to replace wire bonding. The goal of 3D interconnect is to use TSVs to enable wafer-to-wafer or die-to-wafer connectivity. TSVs can be integrated before or after a transistor is fabricated [1]. In a general application, Cu-filled TSVs establish a connection between two metal layers [2]. To thin wafers, wafers are bonded to a handle and then ground from the backside to remove the bulk of unwanted Si. Once the bulk of Si is removed, TSVs from the backside of the wafer can be exposed by using chemical mechanical polishing (CMP) or other chemical processes. Mechanical grinding is the current state of the art for bulk Si removal. The backgrind process has been performed reliably on the Okamoto GDM300. This tool comes equipped with edge trim and wafer cleaning stations. It can grind wafers in two steps and fine-polish ground wafers in two steps. The Okamoto SPP800S CMP tool is then utilized to expose TSVs after grinding. The backgrinding process is set up to remove Si nearly to the bottom of TSV, leaving behind a surface with a mirror finish. The C
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