Material Science and the Electronic Packaging Roadmap
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Introduction The National Technology Roadmap' forecasts significant increases in performance for silicon devices over the next several years continuing the pace of the last 25 years. As the complexity and performance of the silicon have increased, so has the cost to manufacture the supporting packages. However, continued growth of the industry demands that package costs be held under control. A requirement of the Roadmap is a need for a significant lowering of cost over the period. On a per lead basis: for example, for cost/performance products in 1995 the range in per pin cost is 1.4-8 cents. These costs must move to 1 - 3 cents per lead over the next 15 years, while lead count increases from a few hundred to a few thousand. These costs will not be achievable unless we change how materials are developed and deployed to the market. The requirements of the Roadmap for cost/performance products include power going to 55 watts. But, more importantly, there will be a need to handle power distribution at much higher frequencies (i.e. 300500 Mhz). Many chips will have high I/O counts, not only to deal with their functionality, but to provide more power and ground connections. The issue of power distribution and the need to minimize the space required to connect and fan out the connections of a package have led, as forecasted in the Roadmap, to the need for area array packages and chips (flip chips). The implication of these various requirements to the materials community is increased demand on materials, their integration to complex systems and the management of their costs. Significant improvements will be required in the understanding of the fundamental material properties and how to manipulate them for specific applications. Consensus on common approaches will lead to more effective use of resources at the Universities, National Labs and the various consortia, all to the benefit of the users.
Key Components of Successful Integration The successful integration of materials for future packaging applications will require detailed models at all levels from chip to system board. These models must predict the interrelationships among the material properties required and the functional performance, manufacturability and cost of the total system. Extensive effort in validation of the materials is required. This includes identifying the key variables that affect the specific functional requirement placed on the material. Appropriate metrologies and gage capabilities will be needed to support the systematic collection of the data on the key variables. The industry will benefit from a narrowing of the overall solution set and through cooperative efforts among suppliers and users. In the next sections we look at a case study of flip chip on a laminate substrate (such as a PCMCIA card) to illustrate these concepts for successful integration.
Flip Chip on Organic Laminate Carrier43 Flip chips on organic substrates (see Fig. 1) meet many of the future needs of the Roadmap: "* Flip chips provide a low inductance connection (power m
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