Mechanical and Electro-Mechanical Stress Effects on Performance of Flexible IZO TFTs
- PDF / 486,186 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 4 Downloads / 204 Views
Mechanical and Electro-Mechanical Stress Effects on Performance of Flexible IZO TFTs
T. L. Alford, Anil Indluru*, and Rajitha N. P. Vemuri School for Engineering of Matter, Transport, and Energy, Arizona State University, AZ 85287, U.S.A.
ABSTRACT This study reports the influence of electrical and mechanical stresses on indium zinc oxide (IZO) thin film transistors (TFTs).The deformation is introduced by mounting the samples on cylindrical structures of varying radii creating tensile or compressive strains. The mechanical stresses are parallel and perpendicular to the length of the channel layer. Results reveal that, when the stresses are parallel to the channel length, mobilities increase under tensile stresses and reduce under compressive stresses; while, the effect on sub-threshold is contrary to this. However no changes are observed for mobilities and sub-threshold swings when the stresses are perpendicular to the channel length. The TFTs exhibit stability under the electromechanical stressing with no device failure observed over prolonged stress times. INTRODUCTION Amorphous Si based TFTs have for decades dominated the large area electronics market. More recently amorphous mixed oxide TFTs are being established as a ligament replacement owing to their high mobility, and transparency [1]. As large area electronics fabricated on flexible substrates is going to be the industry’s standard, extensive research is to be performed on the stability of the structures under simultaneous mechanical stresses and electrical bias. Polyethylene napthalate (PEN) is used as a substrate due to his flexibility. Previously, results of mechanical stability of a-Si:H transistors fabricated on polymer substrates has been reported [2]. On the topic of IZO based transistors, no mechanical stability study has been reported. However, this study provides understanding of the IZO based TFTs under electromechanical stresses, which serves as a practical stress scenario for large area electronics fabricated on polymer substrates. Tensile and compressive stresses in directions parallel and perpendicular to the length of the channel are used by mounting the transistors on the outer and inner radii of cylindrical tubes of varying radii. The impact on the transistor currents, especially in the off region (Ioff), the mobilities (µ), and subthreshold swing (S) have been reported and the underlying mechanism has been elucidated. EXPERIMENTAL DETAILS Bottom gate staggered structured IZO TFTs were fabricated on PEN substrate of thickness 125 µm. A molybdenum layer of thickness 150 nm was sputtered as the gate electrode. A 100 nm thick SiO2 was deposited as gate dielectric and a 50 nm thick IZO formed the channel layer. A 100 nm layer of SiO2 was deposited at 200 °C over the channel and served as an interlayer
* Current address: Intel Corporation, 5000 W Chandler Blvd., Chandler, AZ 85226, U.S.A.
dielectric. The channel region was patterned and molybdenum was sputtered to form source and drain contacts. Indium-tin oxide was deposited, and patterned
Data Loading...
