Mechanical Scaling Trends and Methods to Improve Reliability of Packaged Interconnect Structures
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Mechanical Scaling Trends and Methods to Improve Reliability of Packaged Interconnect Structures Michael W. Lane, Abigail Roush and Stephen E. Callahan Emory & Henry College, Chemistry Department, PO Box 947, Emory, VA 24327 ABSTRACT Low dielectric constant (low-k) materials are currently being incorporated into advanced microelectronic devices to improve or maintain performance. As the dielectric constant is reduced, so are its mechanical properties. These reduced properties have recently been related to chip-package interaction (CPI) failures. Significant effort has focused on eliminating CPI failures through engineering of copper crackstop structures. However, published data suggests that crackstop engineering needs to occur at each technology node to ensure CPI reliability. In this study, the focus is on repairing interfacial delaminations with chemistry specific coupling agents rather than attempting to stop them with a specially designed crackstop structure. Critical adhesion values and corrosion resistance of the repaired interfaces are compared to the original interface. The application of the repair chemistry in an integrated structure is discussed along with the potential impact on reliability. INTRODUCTION Chip-package Interaction and Microelectronic Scaling Trends The use of low dielectric constant materials has become widespread in semiconductor manufacturing. However, several mechanical issues have been reported due to lowered strengths and stiffness of the lower-k dielectrics.[see e.g. 1,2,3] Among these issues are chip package interaction failures where delaminations that are initiated along the die edge –often during mechanical saw dicing– propagate after being packaged. During thermal excursions, a packaged die often must pass several hundred or a thousand cycles from sub 0 oC to greater than 100 oC. Differences in stiffness and thermal expansion of the varying parts result in high stresses on the die edge that may result in defect growth. The energy supplied by the package to the die has been shown to increase with increasing delamination length as shown schematically in Figure 1a (after [3]). If a delamination of sufficient length exists prior to packaging, the energy applied to the die edge during thermal cycling will be larger than the interfacial adhesion, and the delamination will grow. As the delamination grows, the energy supplied by the package will increase until a steady state is reached. The delamination will continue to grow until it reaches the crackstop that separates the active portion of the die from the dicing channel where the delamination originates. If the crackstop toughness is lower than the energy supplied by the package, chip failure will occur due to the delamination entering the active portion of the die. The crackstop is the main design structure whose purpose is to stop delaminations from entering the active portion of the chip. The crackstop is a monolithic metal structure that surrounds the active portion of the die and separates the functional and nonfun
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