Materials and scaling effects on on-chip interconnect reliability
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Materials and scaling effects on on-chip interconnect reliability C.-K. Hu, E. G. Liniger, L. M. Gignac, G. Bonilla, D. Edelstein, IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, [email protected], Tel: (914)-945-2378 ABSTRACT Scaling effects on Cu microstructure, resistivity, dielectric materials, and electromigration (EM) and time dependent dielectric break down (TDDB) reliabilities for Cu interconnects were reviewed. A simple empirical model of Cu resistivity related to Cu line area was presented. Cu line microstructures containing small grains mixed with large bamboo grains in Cu damascene lines from technology nodes below 65 nm were observed. As predicted in previous work, the EM lifetime was found to degrade by about 50% for every new generation even for the same current density. The Cu grain size was found to have a large impact on pure Cu and Cu alloy EM lifetime and activation energy Ea. Ea for pure Cu line capped with selective electroless CoWP on near-bamboo, bamboo-polycrystalline, to polycrystalline only line grain structures was reduced from 2.2 eV to 1.7 eV to 0.75 eV, respectively. Ea for 40 nm wide bamboopolycrystalline lines capped with selective chemical vapor deposition (CVD) Co was found to be 1.7 eV. Using pure Cu and Cu(Al) or Cu(Mn) diluted impurity seed layers in 40 nm wide, bamboo-polycrystalline microstructure lines and above 100 nm wide, near bamboo-like grained lines, Cu-alloy lines enhanced EM lifetimes and increased QEM from 0.9 to 1. eV and 1.0 to 1.2 eV, respectively, compared to pure Cu lines. Inter-level TDDB testing on vias connecting M1 to M2 with a via chamfer angle that varied from 58o to 81o have very similar performance with intra-level M2 data with no vias tested at the same field. This result combined with the data from a separate study, which allowed the chamfer path to be isolated from the M2-level path, suggested that the failure took place preferentially along the weak cap/ILD interface at M2 and not at the via chamfer. TDDB acceleration data indicated that the root E model was overly conservative and a more aggressive model provided a better fit to the data. TDDB lifetimes correlated fairly well with the percentage of porosity in the dielectric materials. INTRODUCTION As dimensions continue to shrink in back-end-of-line (BEOL) on-chip Cu interconnect structures by a factor of 0.7 with every new generation, the integrated circuit (IC) chips now have devices with dimensions in the tens of nanometers (nm). The types of materials used and the profile dimensional controls of lines, vias and via chamfer have become increasingly critical to ensure time dependent dielectric break down (TDDB) and electromigration (EM) reliability. Cu metallization and dielectric (ILD) with an ultra-low dielectric constant κ (ULK) are still the up-front choices for the 10 nm technology node and beyond. To reduce the RC delay in IC chips, a κ material with more porosity has been implemented for most new technology nodes. For Cu lines in the 45 nm node and beyond, significant changes i
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