Circuit-Level and Layout-Specific Interconnect Reliability Assessments
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Circuit-Level and Layout-Specific Interconnect Reliability Assessments S.P. Hau-Riege1, C.V. Thompson1, C.S. Hau-Riege1, V.K. Andleigh1, Y. Chery2, and D. Troxel2 1 Department of Materials Science and Engineering, M.I.T., Cambridge, MA 2 Department of Electrical Engineering and Computer Science, M.I.T., Cambridge, MA
ABSTRACT We have developed a methodology and a prototype tool for making computationally efficient circuit-level assessments of interconnect reliability. A key component of this process has been the development of simple analytic models that relate the reliability of the complex structures in layouts to the simpler straight, junction-free lines of uniform width that are typically used in lifetime tests. We have considered interconnect trees as the fundamental reliability units, where trees can have multiple junctions and limbs, and can also have width variations. We have developed analytic methods for identifying trees which are immune to failure, and have demonstrated that computationally simple techniques lead to the identification of a large fraction of the trees in a circuit as immune to failure (i.e., that they are `immortal'). These trees therefore need not be considered in further analyses. Using simulations and analytic treatments we have also developed default models which allow estimation of the reliability of the remaining trees. These models have been tested and validated them through experiments on simple tree structures with junctions and line-width transitions. Our prototype circuit-level reliability analysis tool projects the reliability of circuits based on specific layouts, and provides a rank listing of the reliability of mortal trees. This allows the user to accept the assessment as is, to carry out more accurate but computationally-intensive analyses of the least reliable trees, or to modify the layout or process to address reliability concerns and reanalyze the reliability. INTRODUCTION In today’s Si integrated circuit (IC) technology, several meters of metal interconnects are required to build a single high-performance circuit, so that in each IC many millions of metal segments exist. These metallic circuit elements are a great reliability concern owing mainly to electromigration. This concern increases with the level of integration, with each new generation of Si technology requiring the use of a larger number of narrower interconnects, stressed at everhigher current densities. Laid-out integrated circuits often have interconnects with junctions. In carrying out circuitlevel reliability assessments, it is important to be able to assess the reliability of these more complex shapes, generally referred to as 'trees'. An interconnect tree consists of continuously connected high-conductivity metal within one layer of metallization. Trees terminate at diffusion barriers at vias and contacts, and, in the general case, can have more than one terminating branch when they include junctions. An example of an interconnect tree is shown in figure 1 (a). Most modeling and experimental characte
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